| /prebuilts/clang/host/linux-x86/clang-4691093/include/llvm/CodeGen/ |
| LiveVariables.h | 131 const TargetRegisterInfo *TRI;
203 if (MI.addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
239 if (MI.addRegisterDead(IncomingReg, TRI, AddIfNotFound))
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| ResourcePriorityQueue.h | 60 const TargetRegisterInfo *TRI;
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| /external/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 52 const TargetRegisterInfo *TRI;
117 /// This is the smallest value returned by TRI->getCostPerUse(Reg) for all
126 /// same cost according to TRI->getCostPerUse().
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| RegisterScavenging.h | 33 const TargetRegisterInfo *TRI;
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| VirtRegMap.h | 43 const TargetRegisterInfo *TRI;
86 const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
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| /external/llvm/lib/CodeGen/ |
| BranchFolding.h | 37 const TargetRegisterInfo *tri, MachineModuleInfo *mmi,
103 const TargetRegisterInfo *TRI;
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| MachineCopyPropagation.cpp | 40 const TargetRegisterInfo *TRI;
87 const TargetRegisterInfo &TRI) {
90 for (MCSubRegIterator SR(Reg, &TRI, true); SR.isValid(); ++SR)
111 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
117 removeRegsFromMap(AvailCopyMap, SI->second, *TRI);
130 unsigned Def, const TargetRegisterInfo *TRI) {
137 if (!TRI->isSubRegister(PreviousSrc, Src))
139 unsigned SubIdx = TRI->getSubRegIndex(PreviousSrc, Src);
140 return SubIdx == TRI->getSubRegIndex(PreviousDef, Def);
160 if (!isNopCopy(PrevCopy, Src, Def, TRI))
[all...] |
| RegisterPressure.cpp | 57 const TargetRegisterInfo *TRI) {
61 dbgs() << TRI->getRegPressureSetName(i) << "=" << SetPressure[i] << '\n';
70 void RegisterPressure::dump(const TargetRegisterInfo *TRI) const {
72 dumpRegSetPressure(MaxSetPressure, TRI);
75 dbgs() << PrintVRegOrUnit(P.RegUnit, TRI);
83 dbgs() << PrintVRegOrUnit(P.RegUnit, TRI);
95 dumpRegSetPressure(CurrSetPressure, TRI);
97 P.dump(TRI);
100 void PressureDiff::dump(const TargetRegisterInfo &TRI) const {
105 dbgs() << sep << TRI.getRegPressureSetName(Change.getPSet()
[all...] |
| TargetSchedule.cpp | 283 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
284 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
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| /external/llvm/lib/Target/AMDGPU/ |
| R600EmitClauseMarkers.cpp | 187 const R600RegisterInfo &TRI = TII->getRegisterInfo();
192 TRI.isPhysRegLiveAcrossClauses(MOI->getReg()))
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| R600ExpandSpecialInstrs.cpp | 71 const R600RegisterInfo &TRI = TII->getRegisterInfo();
179 const R600RegisterInfo &TRI = TII->getRegisterInfo();
187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
200 const R600RegisterInfo &TRI = TII->getRegisterInfo();
203 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
206 bool Mask = (Chan != TRI.getHWRegChan(DstReg));
230 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
231 (TRI.getEncodingValue(Src1) & 0xff) < 127)
232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1))
[all...] |
| R600MachineScheduler.h | 30 const R600RegisterInfo *TRI;
70 DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
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| SIFixSGPRCopies.cpp | 115 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) {
122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
130 const SIRegisterInfo &TRI,
138 TRI.getPhysRegClass(SrcReg);
141 // SrcRC = TRI.getSubRegClass(SrcRC, Copy.getOperand(1).getSubReg());
146 TRI.getPhysRegClass(DstReg);
153 const SIRegisterInfo &TRI) {
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC);
159 const SIRegisterInfo &TRI) {
[all...] |
| SIFrameLowering.cpp | 64 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
75 unsigned PreloadedScratchWaveOffsetReg = TRI->getPreloadedValue(
80 PreloadedPrivateBufferReg = TRI->getPreloadedValue(
100 = TRI->getPreloadedValue(MF, SIRegisterInfo::FLAT_SCRATCH_INIT);
106 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1);
110 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0);
155 if (ScratchRsrcReg == TRI->reservedPrivateSegmentBufferReg(MF)) {
174 if (ScratchWaveOffsetReg == TRI->reservedPrivateSegmentWaveByteOffsetReg(MF)) {
196 TRI->isSubRegisterEq(ScratchRsrcReg, Reg))
209 assert(!TRI->isSubRegister(ScratchRsrcReg, ScratchWaveOffsetReg))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonBlockRanges.h | 140 const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI);
144 : Map(M), TRI(I) {}
149 const TargetRegisterInfo &TRI;
161 const TargetRegisterInfo &TRI;
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| RDFCopy.cpp | 46 const TargetRegisterInfo &TRI = DFG.getTRI();
47 if (TRI.getMinimalPhysRegClass(DstR.Reg) !=
48 TRI.getMinimalPhysRegClass(SrcR.Reg))
|
| /external/llvm/lib/Target/X86/ |
| X86ExpandPseudo.cpp | 46 const X86RegisterInfo *TRI;
151 unsigned StackPtr = TRI->getStackRegister();
257 TRI = STI->getRegisterInfo();
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| X86FixupBWInsts.cpp | 185 auto *TRI = &TII->getRegisterInfo();
190 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg);
253 auto *TRI = &TII->getRegisterInfo();
254 if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) !=
255 TRI->getSubRegIndex(NewDestReg, OldDest.getReg()))
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| X86SelectionDAGInfo.cpp | 29 // We cannot use TRI->hasBasePointer() until *after* we select all basic
38 const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>(
40 unsigned BaseReg = TRI->getBaseRegister();
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| X86WinAllocaExpander.cpp | 61 const X86RegisterInfo *TRI;
185 } else if (MI.modifiesRegister(StackPtr, TRI)) {
276 TRI = STI->getRegisterInfo();
277 StackPtr = TRI->getStackRegister();
278 SlotSize = TRI->getSlotSize();
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| LiveVariables.h | 146 const TargetRegisterInfo *TRI;
211 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
247 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| ExecutionDepsFix.cpp | 113 const TargetRegisterInfo *TRI;
161 /// Translate TRI register number to an index into our smaller tables of
453 TRI = MF->getTarget().getRegisterInfo();
474 AliasMap.resize(TRI->getNumRegs(), -1);
476 for (const unsigned *AI = TRI->getOverlaps(RC->getRegister(i)); *AI; ++AI)
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| LocalStackSlotAllocation.cpp | 90 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
95 if (!TRI->requiresVirtualBaseRegisters(MF) || LocalObjectCount == 0)
206 const TargetRegisterInfo *TRI) {
213 if (TRI->isFrameOffsetLegal(MI, Offset))
229 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
293 if (TRI->needsFrameBaseReg(MI, LocalOffsets[FrameIdx])) {
310 MI, TRI)) {
320 int64_t InstrOffset = TRI->getFrameIndexInstrOffset(MI, idx);
321 const TargetRegisterClass *RC = TRI->getPointerRegClass();
331 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx
[all...] |
| VirtRegMap.cpp | 58 TRI = mf.getTarget().getRegisterInfo();
82 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
83 E = TRI->regclass_end(); I != E; ++I)
85 TRI->getAllocatableSet(mf, *I)));
126 return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
227 unsigned NumRegs = TRI->getNumRegs();
238 BitVector Allocatable = TRI->getAllocatableSet(*MF);
243 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
308 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
320 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true)
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 55 const TargetRegisterInfo *TRI = nullptr;
121 /// This is the smallest value returned by TRI->getCostPerUse(Reg) for all
130 /// same cost according to TRI->getCostPerUse().
|
