| /external/libdrm/etnaviv/ |
| etnaviv_drmif.h | 70 /* bo flags: */
78 /* bo access flags: (keep aligned to ETNA_PREP_x) */
119 struct etna_bo *etna_bo_ref(struct etna_bo *bo);
120 void etna_bo_del(struct etna_bo *bo);
121 int etna_bo_get_name(struct etna_bo *bo, uint32_t *name);
122 uint32_t etna_bo_handle(struct etna_bo *bo);
123 int etna_bo_dmabuf(struct etna_bo *bo);
124 uint32_t etna_bo_size(struct etna_bo *bo);
125 void * etna_bo_map(struct etna_bo *bo);
126 int etna_bo_cpu_prep(struct etna_bo *bo, uint32_t op)
182 struct etna_bo *bo; member in struct:etna_reloc
[all...] |
| /external/libdrm/omap/ |
| omap_drm.c | 60 /* The handle_table is used to track GEM bo handles associated w/
66 * to an invalid handle (and possible a GEM bo that is already
167 struct omap_bo *bo = NULL; local
168 if (!drmHashLookup(dev->handle_table, handle, (void **)&bo)) {
170 bo = omap_bo_ref(bo);
172 return bo;
179 struct omap_bo *bo = calloc(sizeof(*bo), 1); local
180 if (!bo) {
200 struct omap_bo *bo = NULL; local
291 struct omap_bo *bo = NULL; local
325 struct omap_bo *bo = NULL; local
[all...] |
| /external/libdrm/radeon/ |
| radeon_cs_gem.c | 176 struct radeon_bo *bo,
181 struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
191 /* in one CS a bo can only be in read or write domain but not
203 if this bo is for sure not in this cs.*/
204 if ((atomic_read((atomic_t *)radeon_gem_get_reloc_in_cs(bo)) & cs->id)) {
205 /* check if bo is already referenced.
207 * it often relocates same shared dma bo again. */
212 if (reloc->handle == bo->handle) {
265 reloc->handle = bo->handle;
270 radeon_bo_ref(bo);
344 bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root; local
[all...] |
| radeon_cs_int.h | 6 struct radeon_bo_int *bo; member in struct:radeon_cs_space_check
39 struct radeon_bo *bo,
|
| /external/libdrm/tests/exynos/ |
| exynos_fimg2d_event.c | 97 * potentially remove a BO which the engine still operates on.
100 * Also any subsequent BO allocations fail then with:
210 struct exynos_bo *bo; local
285 bo = exynos_bo_create(dev, bufw * bufh * 4, 0);
286 if (bo == NULL) {
287 fprintf(stderr, "error: failed to create bo\n");
299 img.bo[0] = bo->handle;
313 exynos_bo_destroy(bo);
|
| /external/libxcam/xcore/ |
| drm_display.cpp | 390 const drm_intel_bo* bo = bo_buf->get_bo (); local
391 XCAM_ASSERT (bo);
392 bo_handle = bo->handle;
511 drm_intel_bo *bo = NULL; local
526 XCAM_LOG_DEBUG ("DrmDisplay only support dma buffer conversion to drm bo by now");
530 bo = drm_intel_bo_gem_create_from_prime (_buf_manager, dma_fd, video_info.size);
531 if (bo == NULL) {
532 XCAM_LOG_WARNING ("convert dma fd to drm bo failed");
535 bo_data = new DrmBoData (self, bo);
550 drm_intel_bo *bo = drm_intel_bo_alloc local
560 drm_intel_bo *bo = NULL; local
[all...] |
| /external/mesa3d/src/egl/drivers/dri2/ |
| platform_drm.c | 49 struct gbm_bo *bo; local
56 bo = dri2_surf->current->bo;
63 return bo;
67 release_buffer(struct gbm_surface *_surf, struct gbm_bo *bo)
74 if (dri2_surf->color_buffers[i].bo == bo) {
197 if (dri2_surf->color_buffers[i].bo)
198 gbm_bo_destroy(dri2_surf->color_buffers[i].bo);
233 if (dri2_surf->back->bo == NULL
270 struct gbm_dri_bo *bo; local
392 struct gbm_dri_bo *bo; local
526 struct gbm_dri_bo *bo; local
560 struct gbm_dri_bo *bo; local
[all...] |
| /external/mesa3d/src/gallium/auxiliary/pipebuffer/ |
| pb_bufmgr_slab.c | 92 struct pb_buffer *bo; member in struct:pb_slab
219 pb_reference(&slab->bo, NULL);
259 return pb_validate(buf->slab->bo, vl, flags);
268 pb_fence(buf->slab->bo, fence);
278 pb_get_base_buffer(buf->slab->bo, base_buf, offset);
312 slab->bo = mgr->provider->create_buffer(mgr->provider, mgr->slabSize, &mgr->desc);
313 if(!slab->bo) {
320 slab->virtual = pb_map(slab->bo,
327 pb_unmap(slab->bo);
329 numBuffers = slab->bo->size / mgr->bufSize
[all...] |
| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| etnaviv_resource.c | 207 struct etna_bo *bo = etna_bo_new(screen->dev, size, flags); local
208 if (unlikely(bo == NULL)) {
213 rsc->bo = bo;
220 void *map = etna_bo_map(bo);
285 if (rsc->bo)
286 etna_bo_del(rsc->bo);
327 rsc->bo = etna_screen_bo_from_handle(pscreen, handle, &level->stride);
328 if (!rsc->bo)
342 /* The DDX must give us a BO which conforms to our padding size
[all...] |
| /external/mesa3d/src/gallium/drivers/ilo/ |
| ilo_resource.c | 295 struct intel_bo *bo; local
297 bo = intel_winsys_alloc_bo(is->dev.winsys, name,
301 if (bo && (tex->image.tiling == GEN6_TILING_X ||
306 if (intel_bo_set_tiling(bo, tiling, tex->image.bo_stride)) {
307 intel_bo_unref(bo);
308 bo = NULL;
311 if (!bo)
314 intel_bo_unref(tex->vma.bo);
315 ilo_vma_set_bo(&tex->vma, &is->dev, bo, 0);
353 struct intel_bo *bo; local
385 struct intel_bo *bo; local
444 struct intel_bo *bo; local
600 struct intel_bo *bo; local
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/ |
| nouveau_mm.c | 44 struct nouveau_bo *bo; member in struct:mm_slab
106 /* size of bo allocation for slab with chunks of (1 << chunk_order) bytes */
136 slab->bo = NULL;
139 &slab->bo);
162 /* @return token to identify slab or NULL if we just allocated a new bo */
165 uint32_t size, struct nouveau_bo **bo, uint32_t *offset)
175 bo);
202 nouveau_bo_ref(slab->bo, bo);
273 nouveau_bo_ref(NULL, &slab->bo);
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/nv30/ |
| nv30_state_validate.c | 123 rbo = nv30_miptree(rsf->base.texture)->base.bo;
124 zbo = nv30_miptree(zsf->base.texture)->base.bo;
143 struct nouveau_bo *bo = nv30_miptree(sf->base.texture)->base.bo; local
146 PUSH_MTHDl(push, NV30_3D(COLOR1_OFFSET), BUFCTX_FB, bo, sf->offset,
153 struct nouveau_bo *bo = nv30_miptree(sf->base.texture)->base.bo; local
156 PUSH_MTHDl(push, NV40_3D(COLOR2_OFFSET), BUFCTX_FB, bo, sf->offset,
164 struct nouveau_bo *bo = nv30_miptree(sf->base.texture)->base.bo; local
[all...] |
| nv30_winsys.h | 23 PUSH_RELOC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, uint32_t offset,
26 nouveau_pushbuf_reloc(push, bo, offset, flags, vor, tor);
44 struct nouveau_bo *bo, uint32_t access)
46 nouveau_bufctx_refn(bufctx(push), bin, bo, access); local
51 struct nouveau_bo *bo, uint32_t offset, uint32_t access)
54 bo, offset, access | NOUVEAU_BO_LOW, 0, 0)->priv = NULL; local
55 PUSH_DATA(push, bo->offset + offset);
60 struct nouveau_bo *bo, uint32_t access, uint32_t vor, uint32_t tor)
63 bo, 0, access | NOUVEAU_BO_OR, vor, tor)->priv = NULL; local
64 if (bo->flags & NOUVEAU_BO_VRAM
76 bo, data, access | NOUVEAU_BO_OR, vor, tor)->priv = NULL; local
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| nv50_state_validate.c | 39 struct nouveau_bo *bo; local
48 bo = mt->base.bo;
61 if (likely(nouveau_bo_memtype(bo))) {
|
| nv50_vbo.c | 221 struct nouveau_bo *bo; local
231 &bo);
234 NOUVEAU_BO_RD, bo);
266 struct nouveau_bo *bo; local
270 base, size, &bo);
272 BCTX_REFN_bo(nv50->bufctx_3d, 3D_VERTEX_TMP, bo_flags, bo);
640 PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
645 nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
654 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
666 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes)
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| nve4_compute.c | 368 struct nouveau_bo *bo = nvc0->screen->uniform_bo; local
375 PUSH_DATAh(push, bo->offset + base);
376 PUSH_DATA (push, bo->offset + base);
519 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
524 nouveau_pushbuf_data(push, res->bo, offset,
659 PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
663 nouveau_pushbuf_data(push, res->bo, offset,
676 nouveau_pushbuf_data(push, res->bo, offset + 8,
841 struct nouveau_bo *bo = screen->parm; local
846 ret = nouveau_bo_map(bo, NOUVEAU_BO_RDWR, nvc0->base.client)
[all...] |
| /external/mesa3d/src/gallium/drivers/vc4/kernel/ |
| vc4_drv.h | 39 struct drm_gem_cma_object **bo; member in struct:vc4_exec_info
47 /* Current unvalidated indices into @bo loaded by the non-hardware
52 /* This is the BO where we store the validated command lists, shader
121 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
140 * record's uniform BO pointer can provide, and we need to apply relocations
|
| /external/mesa3d/src/gallium/drivers/vc4/ |
| vc4_bufmgr.c | 82 vc4_bo_remove_from_cache(struct vc4_bo_cache *cache, struct vc4_bo *bo)
84 list_del(&bo->time_list);
85 list_del(&bo->size_list);
87 cache->bo_size -= bo->size;
99 struct vc4_bo *bo = NULL; local
102 bo = LIST_ENTRY(struct vc4_bo, cache->size_list[page_index].next,
105 /* Check that the BO has gone idle. If not, then we want to
109 if (!vc4_bo_wait(bo, 0, NULL)) {
114 pipe_reference_init(&bo->reference, 1);
115 vc4_bo_remove_from_cache(cache, bo);
126 struct vc4_bo *bo; local
321 struct vc4_bo *bo; local
415 struct vc4_bo *bo; local
[all...] |
| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| amdgpu_bo.c | 51 struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); local
52 struct amdgpu_winsys *ws = bo->ws;
56 if (p_atomic_read(&bo->num_active_ioctls))
63 if (!os_wait_until_zero_abs_timeout(&bo->num_active_ioctls, abs_timeout))
67 if (bo->is_shared) {
75 r = amdgpu_bo_wait_for_idle(bo->bo, timeout, &buffer_busy);
88 for (idle_fences = 0; idle_fences < bo->num_fences; ++idle_fences) {
89 if (!amdgpu_fence_wait(bo->fences[idle_fences], 0, false))
95 amdgpu_fence_reference(&bo->fences[i], NULL)
159 struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); local
191 struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); local
205 struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf; local
320 struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf; local
366 struct amdgpu_winsys_bo *bo; local
447 struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); local
458 struct amdgpu_winsys_bo *bo = NULL; \/* fix container_of *\/ local
466 struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); local
528 struct amdgpu_winsys_bo *bo = &slab->entries[i]; local
598 struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); local
634 struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); local
675 struct amdgpu_winsys_bo *bo; local
783 struct amdgpu_winsys_bo *bo; local
875 struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(buffer); local
916 struct amdgpu_winsys_bo *bo; local
[all...] |
| /external/mesa3d/src/gallium/winsys/intel/drm/ |
| intel_drm_winsys.c | 65 gem_bo(const struct intel_bo *bo)
67 return (drm_intel_bo *) bo;
94 drm_intel_bo *bo; local
98 bo = drm_intel_bo_alloc_tiled(winsys->bufmgr,
100 if (bo) {
101 drm_intel_bo_get_tiling(bo, &tiling, &swizzle);
102 drm_intel_bo_unreference(bo);
127 * uploaded to, say, the beginning of a bo, we want the first vertex in the
128 * bo to be fetched. One way to do this is to set the base address of the
131 * bo->offset64 + (vb->buffer_offset - vb->stride * N)
282 drm_intel_bo *bo; local
313 drm_intel_bo *bo; local
[all...] |
| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| radeon_drm_cs.c | 129 p_atomic_dec(&csc->relocs_bo[i].bo->num_cs_references);
130 radeon_bo_reference(&csc->relocs_bo[i].bo, NULL);
133 p_atomic_dec(&csc->slab_buffers[i].bo->num_cs_references);
134 radeon_bo_reference(&csc->slab_buffers[i].bo, NULL);
198 int radeon_lookup_buffer(struct radeon_cs_context *csc, struct radeon_bo *bo)
200 unsigned hash = bo->hash & (ARRAY_SIZE(csc->reloc_indices_hashlist)-1);
205 if (bo->handle) {
214 if (i == -1 || (i < num_buffers && buffers[i].bo == bo))
217 /* Hash collision, look for the BO in the list of relocs linearly. *
348 struct radeon_bo *bo = (struct radeon_bo*)buf; local
602 struct radeon_bo *bo = cs->csc->slab_buffers[i].bo; local
723 struct radeon_bo *bo = (struct radeon_bo*)_buf; local
[all...] |
| radeon_drm_cs.h | 33 struct radeon_bo *bo; member in struct:radeon_bo_item
92 int radeon_lookup_buffer(struct radeon_cs_context *csc, struct radeon_bo *bo);
102 struct radeon_bo *bo)
104 int num_refs = bo->num_cs_references;
105 return num_refs == bo->rws->num_cs ||
106 (num_refs && radeon_lookup_buffer(cs->csc, bo) != -1);
111 struct radeon_bo *bo)
115 if (!bo->num_cs_references)
118 index = radeon_lookup_buffer(cs->csc, bo);
122 if (!bo->handle
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| intel_buffer_objects.c | 203 drm_intel_bo_references(intel->batch.bo, intel_obj->buffer);
207 /* Replace the current busy bo with fresh data. */
249 if (drm_intel_bo_references(intel->batch.bo, intel_obj->buffer)) {
271 * invalidated, then we can make a new little BO, let them write into that,
272 * and blit it into the real BO at unmap time.
322 if (drm_intel_bo_references(intel->batch.bo, intel_obj->buffer)) {
340 * BO, and we'll copy what they put in there out at unmap or
385 /* Ideally we'd use a BO to avoid taking up cache space for the temporary
506 if (!intel->upload.bo)
510 drm_intel_bo_subdata(intel->upload.bo,
687 drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_obj); local
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_draw.c | 202 /* If indirect, emit a bunch of loads from the indirect BO. */
223 drm_intel_bo *bo = intel_bufferobj_buffer(brw, local
229 brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT, bo,
232 brw_load_register_mem(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo,
236 brw_load_register_mem(brw, GEN7_3DPRIM_START_VERTEX, bo,
240 brw_load_register_mem(brw, GEN7_3DPRIM_BASE_VERTEX, bo,
243 brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
247 brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
294 drm_intel_bo_unreference(brw->vb.buffers[i].bo);
295 brw->vb.buffers[i].bo = NULL
[all...] |
| gen7_sol_state.c | 55 drm_intel_bo *bo; local
78 bo = intel_bufferobj_buffer(brw, bufferobj, start, end - start);
79 assert(end <= bo->size);
84 OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
85 OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, end);
363 if (drm_intel_bo_references(brw->batch.bo, obj->prim_count_bo))
409 /* Gather up the results so far and release the BO. */
|
