| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.cpp | 58 "LDRH/LDRSB/LDRSH/STRH immediate too big (%08x)",
|
| ARMAssembler.h | 82 // LDRH/LDRSB/LDRSH/STRH
125 virtual void LDRSB(int cc, int Rd,
|
| ARMAssemblerProxy.h | 71 // LDRH/LDRSB/LDRSH/STRH
114 virtual void LDRSB(int cc, int Rd,
|
| ARMAssembler.cpp | 301 void ARMAssembler::LDRSB(int cc, int Rd, int Rn, uint32_t offset) {
544 // LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
550 "LDRH/LDRSB/LDRSH/STRH immediate too big (%08x)",
562 "LDRH/LDRSB/LDRSH/STRH immediate too big (%08x)",
|
| ARMAssemblerInterface.h | 93 // LDRH/LDRSB/LDRSH/STRH
165 virtual void LDRSB(int cc, int Rd,
|
| MIPS64Assembler.h | 85 // LDRH/LDRSB/LDRSH/STRH
130 virtual void LDRSB(int cc, int Rd,
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| t16-bad.s | 109 ldst ldrsb
|
| /external/capstone/suite/MC/ARM/ |
| basic-thumb2-instructions.s.cs | 290 0x1f,0xf9,0x00,0xb0 = ldrsb.w r11, [pc, #-0]
357 0x15,0xf9,0x04,0x5c = ldrsb r5, [r5, #-4]
358 0x96,0xf9,0x20,0x50 = ldrsb.w r5, [r6, #32]
359 0x96,0xf9,0x21,0x50 = ldrsb.w r5, [r6, #33]
360 0x96,0xf9,0x01,0x51 = ldrsb.w r5, [r6, #257]
361 0x97,0xf9,0x01,0xe1 = ldrsb.w lr, [r7, #257]
362 0x18,0xf9,0x01,0x10 = ldrsb.w r1, [r8, r1]
363 0x15,0xf9,0x02,0x40 = ldrsb.w r4, [r5, r2]
364 0x10,0xf9,0x32,0x60 = ldrsb.w r6, [r0, r2, lsl #3]
365 0x18,0xf9,0x22,0x80 = ldrsb.w r8, [r8, r2, lsl #2
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ThumbDisassembler.c | 157 { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
324 { "LDRSB", 0xf9900000, 0xfff00000, LDM_REG_IMM12 }, // LDRSB <rt>, [<rn>, {, #<imm12>]}
330 { "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
331 { "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
336 { "LDRSB", 0xf9100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
342 { "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form?
[all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| memory-arm-instructions.txt | 192 # LDRSB (immediate)
194 # CHECK: ldrsb r3, [r4
195 # CHECK: ldrsb r2, [r7, #17
196 # CHECK: ldrsb r1, [r8, #255]!
197 # CHECK: ldrsb r12, [sp], #9
206 # FIXME: LDRSB (label)
211 # LDRSB (register)
213 # CHECK: ldrsb r6, [r5, r4
214 # CHECK: ldrsb r3, [r8, r11]!
215 # CHECK: ldrsb r1, [r2, -r1]
[all...] |
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| memory-arm-instructions.txt | 192 # LDRSB (immediate)
194 # CHECK: ldrsb r3, [r4
195 # CHECK: ldrsb r2, [r7, #17
196 # CHECK: ldrsb r1, [r8, #255]!
197 # CHECK: ldrsb r12, [sp], #9
206 # FIXME: LDRSB (label)
211 # LDRSB (register)
213 # CHECK: ldrsb r6, [r5, r4
214 # CHECK: ldrsb r3, [r8, r11]!
215 # CHECK: ldrsb r1, [r2, -r1]
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_sao_edge_offset_class2_chroma.s | 158 LDRSB r12,[r14,r11] @edge_idx = gi1_table_edge_idx[edge_idx]
161 LDRSB r11,[r6,r12] @pi1_sao_offset_u[edge_idx]
188 LDRSB r12,[r14,r11] @edge_idx = gi1_table_edge_idx[edge_idx]
192 LDRSB r11,[r11,r12] @pi1_sao_offset_v[edge_idx]
232 LDRSB r14,[r14,r11] @edge_idx = gi1_table_edge_idx[edge_idx]
235 LDRSB r11,[r6,r14] @pi1_sao_offset_u[edge_idx]
263 LDRSB r12,[r14,r11] @edge_idx = gi1_table_edge_idx[edge_idx]
267 LDRSB r11,[r14,r12] @pi1_sao_offset_v[edge_idx]
[all...] |
| ihevc_sao_edge_offset_class3_chroma.s | 154 LDRSB r12,[r14,r11] @edge_idx = gi1_table_edge_idx[edge_idx]
157 LDRSB r11,[r6,r12] @pi1_sao_offset_u[edge_idx]
182 LDRSB r12,[r14,r11] @edge_idx = gi1_table_edge_idx[edge_idx]
186 LDRSB r11,[r11,r12] @pi1_sao_offset_v[edge_idx]
224 LDRSB r14,[r14,r11] @edge_idx = gi1_table_edge_idx[edge_idx]
227 LDRSB r11,[r6,r14] @pi1_sao_offset_u[edge_idx]
254 LDRSB r12,[r14,r11] @edge_idx = gi1_table_edge_idx[edge_idx]
258 LDRSB r11,[r14,r12] @pi1_sao_offset_v[edge_idx]
[all...] |
| /external/llvm/test/MC/ARM/ |
| diagnostics.s | 564 ldrsb r0, [r0, #1]!
565 ldrsb r0, [r0, r1]!
566 ldrsb r0, [r0], #1
567 ldrsb r0, [r0], r1
617 @ CHECK-ERRORS: ldrsb r0, [r0, #1]!
620 @ CHECK-ERRORS: ldrsb r0, [r0, r1]!
623 @ CHECK-ERRORS: ldrsb r0, [r0], #1
626 @ CHECK-ERRORS: ldrsb r0, [r0], r1
|
| basic-thumb2-instructions.s | [all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| diagnostic.s | 205 ldst_single_wb_32 ldrsb
206 ldst_single_wb_64 ldrsb
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 74 return ARM::LDRSB;
|
| /external/llvm/test/CodeGen/AArch64/ |
| fast-isel-int-ext.ll | 318 ; CHECK: ldrsb w0, [x0, x1]
340 ; CHECK: ldrsb x0, [x0, x1]
434 ; CHECK: ldrsb w0, [x0, w1, sxtw]
458 ; CHECK: ldrsb x0, [x0, w1, sxtw]
|
| ldst-unsignedimm.ll | 23 ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
41 ; CHECK: ldrsb {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
|
| /external/llvm/test/MC/AArch64/ |
| arm64-tls-relocs.s | 121 ldrsb x29, [x28, #:tprel_lo12_nc:var]
124 // CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
245 ldrsb x29, [x28, #:dtprel_lo12_nc:var]
248 // CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
|
| tls-relocs.s | 129 ldrsb x29, [x28, #:dtprel_lo12_nc:var]
133 // CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
331 ldrsb x29, [x28, #:tprel_lo12_nc:var]
335 // CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
|
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| tables.go | 191 LDRSB
660 LDRSB: "LDRSB",
[all...] |
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| tables.go | 191 LDRSB
660 LDRSB: "LDRSB",
[all...] |
| /external/libhevc/common/arm64/ |
| ihevc_sao_edge_offset_class2_chroma.s | 160 LDRSB x12,[x14,x11] //edge_idx = gi1_table_edge_idx[edge_idx]
163 LDRSB x11,[x6,x12] //pi1_sao_offset_u[edge_idx]
198 LDRSB x12,[x14,x11] //edge_idx = gi1_table_edge_idx[edge_idx]
202 LDRSB x11,[x11,x12] //pi1_sao_offset_v[edge_idx]
250 LDRSB x14,[x14,x11] //edge_idx = gi1_table_edge_idx[edge_idx]
253 LDRSB x11,[x6,x14] //pi1_sao_offset_u[edge_idx]
289 LDRSB x12,[x14,x11] //edge_idx = gi1_table_edge_idx[edge_idx]
293 LDRSB x11,[x14,x12] //pi1_sao_offset_v[edge_idx]
[all...] |
| ihevc_sao_edge_offset_class3_chroma.s | 155 LDRSB x12,[x14,x11] //edge_idx = gi1_table_edge_idx[edge_idx]
158 LDRSB x11,[x6,x12] //pi1_sao_offset_u[edge_idx]
191 LDRSB x12,[x14,x11] //edge_idx = gi1_table_edge_idx[edge_idx]
195 LDRSB x11,[x11,x12] //pi1_sao_offset_v[edge_idx]
241 LDRSB x14,[x14,x11] //edge_idx = gi1_table_edge_idx[edge_idx]
244 LDRSB x11,[x6,x14] //pi1_sao_offset_u[edge_idx]
279 LDRSB x12,[x14,x11] //edge_idx = gi1_table_edge_idx[edge_idx]
283 LDRSB x11,[x14,x12] //pi1_sao_offset_v[edge_idx]
[all...] |
