| /external/libpcap/bpf/net/ |
| bpf_filter.c | 615 * code, that memory accesses are within valid ranges (to the
|
| /external/libxml2/doc/ |
| library.html | 141 accesses. The level of compression on saves can be turned on either globally
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| /external/libxml2/test/schemas/ |
| nvdcve_0.xsd | 133 Network exploitable "user_init" => User accesses attacker
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| /external/llvm/docs/Frontend/ |
| PerformanceTips.rst | 120 lower an under aligned access into a sequence of natively aligned accesses.
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| /external/llvm/include/llvm/Analysis/ |
| ValueTracking.h | 235 /// accesses different objects in each iteration, we don't look through the
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| /external/llvm/lib/Analysis/ |
| AliasAnalysis.cpp | 247 // If CS1 only accesses memory through arguments, check if CS2 references
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| ImplicitNullChecks.cpp | 1 //===-- ImplicitNullChecks.cpp - Fold null checks into memory accesses ----===//
|
| /external/llvm/lib/IR/ |
| Globals.cpp | 191 // executable accesses a variable found in a shared-lib, the main
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| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 241 /// Returns true if the target allows unaligned memory accesses of the
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| AArch64PromoteConstant.cpp | 17 // into different constant pool accesses for each field. A bonus side effect is
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| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 1 //=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
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| ARMISelLowering.h | 270 /// unaligned memory accesses of the specified type. Returns whether it
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonStoreWidening.cpp | 189 // Check if the machine instruction MI accesses any storage aliased with
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| /external/llvm/lib/Target/Mips/ |
| MipsCallingConv.td | 270 // accesses (loads and stores). T8 contains the thread pointer.
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| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetTransformInfo.cpp | 208 // on combining the loads generated for consecutive accesses, and failure to
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 43 // accesses (LARL). Operand 0 is the address.
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| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 406 // used only as address base for memory accesses. If so, it can be
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| X86RegisterInfo.cpp | 171 // frame, this is fine to use it for the address accesses as well.
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| X86WinEHState.cpp | 146 // This pass should only insert a stack allocation, memory accesses, and
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| /external/llvm/lib/Transforms/Instrumentation/ |
| SanitizerCoverage.cpp | 19 // The accesses to Guard are atomic. The rest of the logic is
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| /external/llvm/utils/PerfectShuffle/ |
| PerfectShuffle.cpp | 220 // Seed the table with accesses to the LHS and RHS.
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| /external/ltp/testcases/kernel/device-drivers/v4l/user_space/doc/spec/ |
| c174.htm | 488 permit at least concurrent accesses without data exchange, i. e. panel
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| /external/ltp/testcases/kernel/mem/mmapstress/ |
| mmapstress01.c | 52 * all of whom mmap the same file, make a given number of accesses
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| mmapstress10.c | 49 * all of whom mmap the same file, make a given number of accesses
|
