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full:accesses
(Results
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/libcore/ojluni/src/main/java/java/util/concurrent/
CountedCompleter.java
343
* within this method to ensure thread safety of
accesses
to fields of
Exchanger.java
332
* Element
accesses
use emulation of volatile gets and CAS.
ForkJoinPool.java
218
* properly fences
accesses
, and possibly signals waiting workers
248
* ordering: Slot
accesses
are preceded by a read of base,
351
*
accesses
to workQueues are via indices into the workQueues
[
all
...]
PriorityBlockingQueue.java
[
all
...]
ThreadLocalRandom.java
85
* Random) using a single static instance that
accesses
random
[
all
...]
/libcore/ojluni/src/main/java/java/util/stream/
DoubleStream.java
290
* library chooses. If the action
accesses
shared state, it is
[
all
...]
IntStream.java
285
* library chooses. If the action
accesses
shared state, it is
[
all
...]
/packages/apps/Contacts/src/com/android/contacts/model/
ContactLoader.java
318
// we are not doing any more network or disc
accesses
[
all
...]
/packages/apps/Dialer/java/com/android/contacts/common/model/
ContactLoader.java
232
// we are not doing any more network or disc
accesses
[
all
...]
/packages/apps/UnifiedEmail/src/com/android/mail/ui/
AnimatedAdapter.java
146
* The next action to perform. Do not read or write this. All
accesses
should
[
all
...]
/prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/
ScheduleDAG.h
166
/// \brief Tests if this is an Order dependence between two memory
accesses
/prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/MC/
MCInstrDesc.h
392
/// 2. Memory
accesses
. Use mayLoad/mayStore.
/prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/CodeGen/
ScheduleDAG.h
166
/// \brief Tests if this is an Order dependence between two memory
accesses
/prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/MC/
MCInstrDesc.h
392
/// 2. Memory
accesses
. Use mayLoad/mayStore.
/prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/CodeGen/
ScheduleDAG.h
166
/// \brief Tests if this is an Order dependence between two memory
accesses
/prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/MC/
MCInstrDesc.h
392
/// 2. Memory
accesses
. Use mayLoad/mayStore.
/prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/CodeGen/
ScheduleDAG.h
166
/// \brief Tests if this is an Order dependence between two memory
accesses
/prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/MC/
MCInstrDesc.h
401
/// 2. Memory
accesses
. Use mayLoad/mayStore.
/prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/CodeGen/
ScheduleDAG.h
166
/// \brief Tests if this is an Order dependence between two memory
accesses
/prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/MC/
MCInstrDesc.h
401
/// 2. Memory
accesses
. Use mayLoad/mayStore.
/prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/CodeGen/
ScheduleDAG.h
166
/// \brief Tests if this is an Order dependence between two memory
accesses
/prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/MC/
MCInstrDesc.h
401
/// 2. Memory
accesses
. Use mayLoad/mayStore.
/prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/CodeGen/
ScheduleDAG.h
166
/// \brief Tests if this is an Order dependence between two memory
accesses
/prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/MC/
MCInstrDesc.h
401
/// 2. Memory
accesses
. Use mayLoad/mayStore.
/prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/
ScheduleDAG.h
166
/// \brief Tests if this is an Order dependence between two memory
accesses
Completed in 1154 milliseconds
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