| /external/llvm/test/CodeGen/SystemZ/ |
| int-conv-06.ll | 110 %add2 = add i64 %add1, 524287
111 %ptr = inttoptr i64 %add2 to i16 *
|
| int-conv-07.ll | 100 %add2 = add i64 %add1, 524287
101 %ptr = inttoptr i64 %add2 to i16 *
|
| int-conv-08.ll | 109 %add2 = add i64 %add1, 524287
110 %ptr = inttoptr i64 %add2 to i16 *
|
| int-div-01.ll | 187 %add2 = add i64 %add1, 524287
188 %ptr = inttoptr i64 %add2 to i32 *
|
| int-div-02.ll | 163 %add2 = add i64 %add1, 524287
164 %ptr = inttoptr i64 %add2 to i32 *
|
| int-div-03.ll | 185 %add2 = add i64 %add1, 524287
186 %ptr = inttoptr i64 %add2 to i32 *
|
| int-div-04.ll | 151 %add2 = add i64 %add1, 524287
152 %ptr = inttoptr i64 %add2 to i64 *
|
| int-div-05.ll | 163 %add2 = add i64 %add1, 524287
164 %ptr = inttoptr i64 %add2 to i64 *
|
| vec-combine-01.ll | 33 %add2 = add <4 x i32> %v2, %v3
34 %shuffle = shufflevector <4 x i32> %add1, <4 x i32> %add2,
|
| cond-store-03.ll | 216 %add2 = add i64 %add1, 4096
217 %ptr = inttoptr i64 %add2 to i32 *
|
| int-cmp-05.ll | 198 %add2 = add i64 %add1, 524284
199 %ptr = inttoptr i64 %add2 to i32 *
|
| int-mul-08.ll | 185 %add2 = add i64 %add1, 524287
186 %ptr = inttoptr i64 %add2 to i64 *
|
| /external/llvm/test/Transforms/Reassociate/ |
| xor_reassoc.ll | 145 %add2 = add i32 %add, %or1
146 ret i32 %add2
|
| /external/swiftshader/third_party/LLVM/test/Transforms/InstSimplify/ |
| compare.ll | 74 define i1 @add2(i8 %x, i8 %y) {
75 ; CHECK: @add2
|
| /art/test/442-checker-constant-folding/smali/ |
| TestCmp.smali | 341 ## CHECK-DAG: <<Add2:i\d+>> Add [<<Const5>>,<<Const6>>]
342 ## CHECK-DAG: <<Add3:i\d+>> Add [<<Add1>>,<<Add2>>]
386 ## CHECK-DAG: <<Add2:i\d+>> Add [<<Const5>>,<<Const6>>]
387 ## CHECK-DAG: <<Add3:i\d+>> Add [<<Add1>>,<<Add2>>]
|
| /external/libvpx/libvpx/vpx_dsp/mips/ |
| deblock_msa.c | 661 v4i32 add0, add1, add2, add3; local
685 ADD2(sum0_h, dst_r_h, sum1_h, dst_l_h, sum0_h, sum1_h);
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| haddsub-undef.ll | 304 %add2 = fadd float %vecext2, %vecext3
305 %vecinit2 = insertelement <8 x float> %vecinit1, float %add2, i32 1
441 %add2 = add i32 %vecext2, %vecext3
442 %vecinit2 = insertelement <8 x i32> %vecinit1, i32 %add2, i32 1
|
| /art/compiler/optimizing/ |
| induction_var_analysis_test.cc | 412 HInstruction* add2 = InsertInstruction( local
415 new (GetAllocator()) HAdd(DataType::Type::kInt32, add1, add2), 0);
420 EXPECT_STREQ("((1) * i + (7)):Int32", GetInductionInfo(add2, 0).c_str());
512 HInstruction* add2 = InsertInstruction( local
526 GetInductionInfo(add2, 0).c_str());
569 HInstruction* add2 = InsertInstruction( local
585 EXPECT_STREQ("geo((2) * 2 ^ i + (100)):Int32", GetInductionInfo(add2, 0).c_str());
[all...] |
| /external/llvm/test/Transforms/LoopReroll/ |
| basic.ll | 24 %add2 = add nsw i32 %i.08, 2
25 %call3 = tail call i32 @foo(i32 %add2) #1
519 %add2 = add nsw i32 %i.08, 2
520 %tmp2b = mul i32 %add2, %z
521 %tmp1b = add i32 %add2, %y
|
| /external/clang/test/OpenMP/ |
| for_simd_codegen.cpp | 503 // CHECK-NEXT: [[ADD2:%.+]] = add nsw i32 [[IV2]], 1
504 // CHECK-NEXT: store i32 [[ADD2]], i32* [[IT_OMP_IV]]
578 // CHECK-NEXT: [[ADD2:%.+]] = add i32 [[IV2]], 1
579 // CHECK-NEXT: store i32 [[ADD2]], i32* [[OMP_IV]]
654 // CHECK-NEXT: [[ADD2:%.+]] = add nsw i64 [[IV2]], 1
655 // CHECK-NEXT: store i64 [[ADD2]], i64* [[OMP_IV]]
|
| parallel_for_simd_codegen.cpp | 460 // CHECK-NEXT: [[ADD2:%.+]] = add nsw i32 [[IV2]], 1
461 // CHECK-NEXT: store i32 [[ADD2]], i32* [[IT_OMP_IV]]
534 // CHECK-NEXT: [[ADD2:%.+]] = add i32 [[IV2]], 1
535 // CHECK-NEXT: store i32 [[ADD2]], i32* [[OMP_IV]]
607 // CHECK-NEXT: [[ADD2:%.+]] = add nsw i64 [[IV2]], 1
608 // CHECK-NEXT: store i64 [[ADD2]], i64* [[OMP_IV]]
|
| simd_codegen.cpp | 357 // CHECK-NEXT: [[ADD2:%.+]] = add nsw i32 [[IV2]], 1
358 // CHECK-NEXT: store i32 [[ADD2]], i32* [[IT_OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[ITER_LOOP_ID]]
416 // CHECK-NEXT: [[ADD2:%.+]] = add i32 [[IV2]], 1
417 // CHECK-NEXT: store i32 [[ADD2]], i32* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]]
472 // CHECK-NEXT: [[ADD2:%.+]] = add nsw i64 [[IV2]], 1
473 // CHECK-NEXT: store i64 [[ADD2]], i64* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]]
[all...] |
| /external/tensorflow/tensorflow/tools/graph_transforms/ |
| transform_utils_test.cc | 679 Output add2 = Add(root.WithOpName("add2"), a_const, a_const); local
685 Output mul2 = Mul(root.WithOpName("output"), mul, add2);
691 TF_ASSERT_OK(RenameNodeInputs(graph_def, {{"a", "b"}}, {"add2"},
698 EXPECT_EQ("a", node_map.at("add2")->input(0));
699 EXPECT_EQ("a", node_map.at("add2")->input(1));
[all...] |
| /external/llvm/test/Transforms/SLPVectorizer/X86/ |
| phi.ll | 82 %add2 = fadd double %G.018, 1.000000e+01
84 %mul3 = fmul double %add2, 4.000000e+00
|
| /external/tensorflow/tensorflow/core/distributed_runtime/ |
| executor_test.cc | 329 auto add2 = test::graph::Add(g.get(), add0, add1); local
330 test::graph::Send(g.get(), add2, "e", BOB, 1, ALICE);
|
