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  /external/llvm/test/MC/Mips/mips32r6/
invalid-mips32-wrong-error.s 10 bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
  /external/llvm/test/MC/Mips/mips64r6/
invalid-mips32-wrong-error.s 9 bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/
mips4-fp.d 22 [0-9a-f]+ <[^>]*> movf.d \$f4,\$f6,\$fcc0
23 [0-9a-f]+ <[^>]*> movf.s \$f4,\$f6,\$fcc0
27 [0-9a-f]+ <[^>]*> movt.d \$f4,\$f6,\$fcc0
28 [0-9a-f]+ <[^>]*> movt.s \$f4,\$f6,\$fcc0
micromips@mips4-fp.d 27 [0-9a-f]+ <[^>]*> 5486 0220 movf\.d \$f4,\$f6,\$fcc0
28 [0-9a-f]+ <[^>]*> 5486 0020 movf\.s \$f4,\$f6,\$fcc0
32 [0-9a-f]+ <[^>]*> 5486 0260 movt\.d \$f4,\$f6,\$fcc0
33 [0-9a-f]+ <[^>]*> 5486 0060 movt\.s \$f4,\$f6,\$fcc0
mips4-fp.l 12 .*:15: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f4,\$f6,\$fcc0'
13 .*:16: Error: opcode not supported on this processor: .* \(.*\) `movf.s \$f4,\$f6,\$fcc0'
17 .*:20: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f4,\$f6,\$fcc0'
18 .*:21: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f4,\$f6,\$fcc0'
  /external/capstone/suite/MC/Sparc/
sparc-fp-instructions.s.cs 42 0x81,0xa8,0x0a,0x24 = fcmps %fcc0, %f0, %f4
43 0x81,0xa8,0x0a,0x44 = fcmpd %fcc0, %f0, %f4
44 0x81,0xa8,0x0a,0x64 = fcmpq %fcc0, %f0, %f4
45 0x81,0xa8,0x0a,0xa4 = fcmpes %fcc0, %f0, %f4
46 0x81,0xa8,0x0a,0xc4 = fcmped %fcc0, %f0, %f4
47 0x81,0xa8,0x0a,0xe4 = fcmpeq %fcc0, %f0, %f4
  /external/llvm/test/MC/Mips/
micromips-movcond-instructions.s 14 # CHECK-EL: movt $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x09]
15 # CHECK-EL: movf $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x01]
21 # CHECK-EB: movt $9, $6, $fcc0 # encoding: [0x55,0x26,0x09,0x7b]
22 # CHECK-EB: movf $9, $6, $fcc0 # encoding: [0x55,0x26,0x01,0x7b]
25 movt $9, $6, $fcc0
26 movf $9, $6, $fcc0
mips-jump-delay-slots.s 55 bc1fl $fcc0, 1332
64 bc1tl $fcc0, 1332
micromips-fpu-instructions.s 62 # CHECK-EL: movt.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x00]
63 # CHECK-EL: movt.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x02]
64 # CHECK-EL: movf.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x00]
65 # CHECK-EL: movf.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x02]
127 # CHECK-EB: movt.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x60]
128 # CHECK-EB: movt.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x60]
129 # CHECK-EB: movf.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x20]
130 # CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20]
188 movt.s $f4, $f6, $fcc0
189 movt.d $f4, $f6, $fcc0
    [all...]
  /external/llvm/test/MC/Mips/mips2/
invalid-mips32.s 22 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
26 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
31 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
33 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
34 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
invalid-mips32r2.s 31 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
33 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
35 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
40 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
42 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
43 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/llvm/test/MC/Mips/mips3/
invalid-mips4.s 12 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
21 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
23 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
invalid-mips5.s 13 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
22 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/llvm/test/CodeGen/Mips/
select.ll 207 ; 32: movt.s $f14, $f12, $fcc0
213 ; 32R2: movt.s $f14, $f12, $fcc0
222 ; 64: movt.s $f13, $f12, $fcc0
226 ; 64R2: movt.s $f13, $f12, $fcc0
244 ; 32: movt.s $f14, $f12, $fcc0
250 ; 32R2: movt.s $f14, $f12, $fcc0
259 ; 64: movt.s $f13, $f12, $fcc0
263 ; 64R2: movt.s $f13, $f12, $fcc0
281 ; 32: movf.s $f14, $f12, $fcc0
287 ; 32R2: movf.s $f14, $f12, $fcc0
    [all...]
fcmp.ll 44 ; 32-C: movf $2, $zero, $fcc0
48 ; 64-C: movf $2, $zero, $fcc0
61 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
78 ; 32-C: movt $2, $zero, $fcc0
82 ; 64-C: movt $2, $zero, $fcc0
95 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
112 ; 32-C: movt $2, $zero, $fcc0
116 ; 64-C: movt $2, $zero, $fcc0
129 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
146 ; 32-C: movf $2, $zero, $fcc0
    [all...]
  /external/llvm/test/CodeGen/Mips/Fast-ISel/
fpcmpa.ll 26 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
47 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
67 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
88 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
108 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
128 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
148 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
168 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
188 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
208 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
    [all...]
  /external/swiftshader/third_party/LLVM/test/CodeGen/SPARC/
2011-01-11-CC.ll 72 ;V9: mov{{e|ne}} %fcc0
87 ;V9: fmovs{{e|ne}} %fcc0
101 ;V9: fmovd{{e|ne}} %fcc0
  /external/llvm/test/CodeGen/Mips/llvm-ir/
select-dbl.ll 147 ; CMOV-32: movt.d $f14, $f12, $fcc0
154 ; CMOV-64: movt.d $f13, $f12, $fcc0
161 ; MM32R3: movt.d $f14, $f12, $fcc0
184 ; CMOV-32: movt.d $f14, $f12, $fcc0
191 ; CMOV-64: movt.d $f13, $f12, $fcc0
198 ; MM32R3: movt.d $f14, $f12, $fcc0
221 ; CMOV-32: movf.d $f14, $f12, $fcc0
228 ; CMOV-64: movf.d $f13, $f12, $fcc0
235 ; MM32R3: movf.d $f14, $f12, $fcc0
258 ; CMOV-32: movf.d $f14, $f12, $fcc0
    [all...]
select-flt.ll 124 ; CMOV-32: movt.s $f14, $f12, $fcc0
131 ; CMOV-64: movt.s $f13, $f12, $fcc0
138 ; MM32R3: movt.s $f14, $f12, $fcc0
161 ; CMOV-32: movt.s $f14, $f12, $fcc0
168 ; CMOV-64: movt.s $f13, $f12, $fcc0
175 ; MM32R3: movt.s $f14, $f12, $fcc0
198 ; CMOV-32: movf.s $f14, $f12, $fcc0
205 ; CMOV-64: movf.s $f13, $f12, $fcc0
212 ; MM32R3: movf.s $f14, $f12, $fcc0
235 ; CMOV-32: movf.s $f14, $f12, $fcc0
    [all...]
  /external/swiftshader/third_party/subzero/tests_lit/assembler/mips32/
encoding_test_fcmp.ll 102 ; ASM: movf $v0, $zero, $fcc0
109 ; DIS-NEXT: 28: 00001001 movf v0,zero,$fcc0
147 ; ASM: movf $v0, $zero, $fcc0
154 ; DIS-NEXT: 48: 00001001 movf v0,zero,$fcc0
192 ; ASM: movt $v0, $zero, $fcc0
199 ; DIS-NEXT: 68: 00011001 movt v0,zero,$fcc0
237 ; ASM: movt $v0, $zero, $fcc0
244 ; DIS-NEXT: 88: 00011001 movt v0,zero,$fcc0
282 ; ASM: movt $v0, $zero, $fcc0
289 ; DIS-NEXT: a8: 00011001 movt v0,zero,$fcc0
    [all...]
  /external/llvm/lib/Target/Sparc/
SparcInstrAliases.td 215 // fb<cond> %fcc0, $imm
220 // fb<cond>,pt %fcc0, $imm
225 // fb<cond>,a %fcc0, $imm
230 // fb<cond>,a,pt %fcc0, $imm
235 // fb<cond>,pn %fcc0, $imm
240 // fb<cond>,a,pn %fcc0, $imm
249 // fmovq<cond> %fcc0, $rs2, $rd
490 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
491 def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
492 def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>
    [all...]
  /external/valgrind/none/tests/mips64/
move_instructions.stdout.exp-BE     [all...]
move_instructions.stdout.exp-LE     [all...]
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/sparc/
hpcvis3.s 75 flcmps %fcc0, %f1, %f3
79 flcmpd %fcc0, %f12, %f14
  /external/llvm/test/CodeGen/SPARC/
2011-01-11-CC.ll 75 ;V9: mov{{e|ne}} %fcc0
90 ;V9: fmovs{{e|ne}} %fcc0
106 ;V9: fmovd{{e|ne}} %fcc0

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