| /toolchain/binutils/binutils-2.27/opcodes/ |
| iq2000-opc.c | 713 /* lui $rt,$hi16 */
716 { { MNEM, ' ', OP (RT), ',', OP (HI16), 0 } },
755 /* andoui $rt,$rs,$hi16 */
758 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } },
761 /* andoui ${rt-rs},$hi16 */
764 { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } },
767 /* orui ${rt-rs},$hi16 */
770 { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } },
773 /* orui $rt,$rs,$hi16 */
776 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } }
[all...] |
| iq2000-desc.c | 429 /* hi16: high 16 bit immediate */
430 { "hi16", IQ2000_OPERAND_HI16, HW_H_UINT, 15, 16,
860 /* lui $rt,$hi16 */
895 /* andoui $rt,$rs,$hi16 */
900 /* andoui ${rt-rs},$hi16 */
905 /* orui ${rt-rs},$hi16 */
910 /* orui $rt,$rs,$hi16 */
[all...] |
| lm32-desc.c | 323 /* hi16: high 16-bit immediate */
324 { "hi16", LM32_OPERAND_HI16, HW_H_UINT, 15, 16,
387 /* andhi $r1,$r0,$hi16 */
567 /* orhi $r1,$r0,$hi16 */
707 /* mvhi $r1,$hi16 */
[all...] |
| m32r-desc.c | 239 { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
279 { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
389 /* hi16: high 16 bit immediate, sign optional */
390 { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
980 /* seth $dr,$hash$hi16 */
[all...] |
| m32r-opinst.c | 410 { INPUT, "hi16", HW_H_HI16, CGEN_MODE_UINT, OP_ENT (HI16), 0, 0 },
[all...] |
| /external/llvm/lib/ExecutionEngine/RuntimeDyld/ |
| RuntimeDyldELF.h | 148 // *HI16 relocations will be added for resolving when we find matching
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUOperands.td | 51 def HI16 : SDNodeXForm<imm, [{
160 def hi16 : PatLeaf<(imm), [{
161 // hi16 predicate - returns true if the immediate has all zeros in the
172 }], HI16>;
|
| /toolchain/binutils/binutils-2.27/gas/ |
| write.h | 57 BFD_RELOC_{LO16,HI16,HI16_S} relocations.
|
| /toolchain/binutils/binutils-2.27/gas/config/ |
| tc-tilepro.c | 225 INSERT_SPECIAL_OP(hi16);
442 /* Take an expression like hi16(x) and turn it into x with
896 /* Extend the expression parser to handle hi16(label), etc.
917 /* hi16, etc. not followed by a paren is just a label with that
[all...] |
| tc-iq2000.c | 531 /* Record a HI16 reloc for later matching with its LO16 cousin. */
551 We need to check for HI16 relocs and queue them up for later sorting. */
579 /* Sort any unmatched HI16 relocs so that they immediately precede
|
| tc-m32r.c | [all...] |
| /external/valgrind/VEX/priv/ |
| host_arm_defs.c | 2939 UInt hi16 = (imm32 >> 16) & 0xFFFF; local
3000 UInt hi16 = (imm32 >> 16) & 0xFFFF; local
3023 UInt hi16 = (imm32 >> 16) & 0xFFFF; local
[all...] |
| /toolchain/binutils/binutils-2.27/include/opcode/ |
| v850.h | 193 /* hi16 bit immediate follows instruction, V850E specific. */
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCJITInfo.cpp | 56 AtI[0] = BUILD_LIS(12, To >> 16); // lis r12, hi16(address)
61 AtI[0] = BUILD_LIS(12, To >> 48); // lis r12, hi16(address)
64 AtI[3] = BUILD_ORIS(12, 12, To >> 16); // oris r12, r12, hi16(address)
|
| PPCInstrInfo.td | 182 def HI16 : SDNodeXForm<imm, [{
237 }], HI16>;
248 }], HI16>;
[all...] |
| /toolchain/binutils/binutils-2.27/cpu/ |
| iq2000.cpu | 401 (name hi16)
406 (handlers (parse "hi16"))
1029 "lui $rt,$hi16"
1030 (+ OP_LUI (f-rs 0) rt hi16)
1031 (set rt (sll hi16 16))
[all...] |
| m32r.cpu | 482 (dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16)
534 (dnh h-hi16 "high 16 bits" ()
708 (name hi16)
711 (type h-hi16)
712 (index f-hi16)
713 (handlers (parse "hi16"))
[all...] |
| mt.opc | 159 else if (strncmp (*strp, "%hi16", 5) == 0)
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | 704 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
715 Binary |= Hi16 & 0xFFF;
716 Binary |= ((Hi16 >> 12) & 0xF) << 16;
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.td | 71 def HI16 : SDNodeXForm<imm, [{
155 return ((N->getZExtValue() & 0xFFFF0000UL) == N->getZExtValue());}], HI16> {
164 return ((N->getZExtValue() & 0xFFFFUL) == 0xFFFFUL);}], HI16> {
846 def : Pat<(i32 imm:$imm), (OR_I_LO (MOVHI (HI16 imm:$imm)), (LO16 imm:$imm))>;
|
| /toolchain/binutils/binutils-2.27/bfd/ |
| mipsbsd.c | 284 "HI16", FALSE, 0, 0x0000ffff, FALSE},
|
| elf32-m32r.c | 294 because there is a carry from the LO16 to the HI16. Here we just save
297 number of HI16 relocs to be associated with a single LO16 reloc. The
298 assembler sorts the relocs to ensure each HI16 immediately precedes its
370 /* Handle an M32R ELF HI16 reloc. */
439 /* Do the HI16 relocation. Note that we actually don't need
[all...] |
| elf32-dlx.c | 39 loader phase we can have the corrected hi16 vale replace the buggous lo16
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinRegisterInfo.cpp | 144 TII.get(BF::LOAD16i), getSubReg(Reg, BF::hi16))
|
| /toolchain/binutils/binutils-2.27/gold/ |
| mips.cc | 5140 reloc_high<size, big_endian> hi16 = *it; local
[all...] |
