/external/libhevc/common/arm64/ |
ihevc_sao_edge_offset_class1.s | 83 LDRB w10,[x3,x9] //pu1_src_top[wd - 1] 89 LDRB w14,[x10] //Load pu1_src[row * src_strd + wd - 1] 99 LDRB w4,[x5,#2] //pu1_avail[2] 106 LDRB w4,[x5,#3] //pu1_avail[3] 123 LDRB w4,[x5,#2] //pu1_avail[2] 260 LDRB w4,[x5,#2] //pu1_avail[2]
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ihevc_intra_pred_filters_luma_mode_11_to_17.s | 140 ldrb w11, [x1], #-1 145 ldrb w12, [x1], #-1 147 ldrb w10, [x1], #-1 149 ldrb w14, [x1], #-1 212 ldrb w11, [x1], #-1 237 ldrb w11, [x1, x20]
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ihevc_sao_band_offset_luma.s | 93 LDRB w11,[x10] 105 LDRB w10,[x9,#-1]
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/external/tremolo/Tremolo/ |
dpen.s | 101 LDRB r7, [r2] 126 LDRB r10,[r8], -r6 @ r10= next=t[chase+bit] r8=chase+bit 143 LDRB r14,[r12,r14,LSR #7] @ r14= t[chase+bit+1+(!bit || t[chase]0x0x80)] 328 LDRB r2, [r4, r2] @ r2 = v = q->val[entry & mask] 372 LDRB r2, [r4], #1 @ r2 = v = *ptr++ 478 LDRB r2, [r0],#1 @ r2 = data[j]
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/external/llvm/test/MC/Disassembler/ARM/ |
memory-arm-instructions.txt | 51 # LDRB (immediate) 53 # CHECK: ldrb r3, [r8] 54 # CHECK: ldrb r1, [sp, #63] 55 # CHECK: ldrb r9, [r3, #4095]! 56 # CHECK: ldrb r8, [r1], #22 57 # CHECK: ldrb r2, [r7], #-19 67 # LDRB (register) 69 # CHECK: ldrb r9, [r8, r5] 70 # CHECK: ldrb r1, [r5, -r1] 71 # CHECK: ldrb r3, [r5, r2] [all...] |
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
memory-arm-instructions.txt | 51 # LDRB (immediate) 53 # CHECK: ldrb r3, [r8] 54 # CHECK: ldrb r1, [sp, #63] 55 # CHECK: ldrb r9, [r3, #4095]! 56 # CHECK: ldrb r8, [r1], #22 57 # CHECK: ldrb r2, [r7], #-19 67 # LDRB (register) 69 # CHECK: ldrb r9, [r8, r5] 70 # CHECK: ldrb r1, [r5, -r1] 71 # CHECK: ldrb r3, [r5, r2] [all...] |
/external/capstone/suite/MC/ARM/ |
basic-thumb2-instructions.s.cs | 289 0x1f,0xf8,0x00,0x90 = ldrb.w r9, [pc, #-0] 300 0x15,0xf8,0x04,0x5c = ldrb r5, [r5, #-4] 301 0x96,0xf8,0x20,0x50 = ldrb.w r5, [r6, #32] 302 0x96,0xf8,0x21,0x50 = ldrb.w r5, [r6, #33] 303 0x96,0xf8,0x01,0x51 = ldrb.w r5, [r6, #257] 304 0x97,0xf8,0x01,0xe1 = ldrb.w lr, [r7, #257] 305 0x18,0xf8,0xff,0x5f = ldrb r5, [r8, #255]! 306 0x15,0xf8,0x04,0x2f = ldrb r2, [r5, #4]! 307 0x14,0xf8,0x04,0x1d = ldrb r1, [r4, #-4]! 308 0x13,0xf8,0xff,0xeb = ldrb lr, [r3], #25 [all...] |
/toolchain/binutils/binutils-2.27/opcodes/ |
epiphany-opc.c | 443 /* ldrb $rd,[$rn,$rm] */ 449 /* ldrb $rd,[$rn],$rm */ 455 /* ldrb $rd6,[$rn6,$direction$rm6] */ 461 /* ldrb $rd6,[$rn6],$direction$rm6 */ 467 /* ldrb $rd,[$rn,$disp3] */ 473 /* ldrb $rd6,[$rn6,$dpmi$disp11] */ 479 /* ldrb $rd6,[$rn6],$dpmi$disp11 */ [all...] |
/external/v8/src/regexp/arm64/ |
regexp-macro-assembler-arm64.cc | 255 __ Ldrb(w10, MemOperand(characters_address, 1, PostIndex)); 336 __ Ldrb(w10, MemOperand(capture_start_address, 1, PostIndex)); 337 __ Ldrb(w11, MemOperand(current_position_address, 1, PostIndex)); 488 __ Ldrb(w10, MemOperand(capture_start_address, 1, PostIndex)); 489 __ Ldrb(w11, MemOperand(current_position_address, 1, PostIndex)); 581 __ Ldrb(w11, MemOperand(x11, w10, UXTW)); 662 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); 675 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); [all...] |
/bionic/libc/arch-arm/cortex-a9/bionic/ |
strcmp.S | 84 use LDRB to load and compare byte by byte until 204 ldrb ip, [r1], #1 211 ldrb ip, [r1], #1 218 ldrb ip, [r1], #1 425 ldrb w2, [wp2]
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/external/llvm/test/CodeGen/AArch64/ |
swifterror.ll | 44 ; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8] 83 ; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8] 258 ; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8] 272 ; CHECK-O0: ldrb [[CODE:w[0-9]+]] 353 ; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8]
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ldst-unscaledimm.ll | 50 ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits 115 ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
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/external/boringssl/src/crypto/fipsmodule/sha/asm/ |
sha256-armv4.pl | 99 @ ldrb $t1,[$inp,#3] @ $i 101 ldrb $t2,[$inp,#2] 102 ldrb $t0,[$inp,#1] 104 ldrb $t2,[$inp],#4 133 ldrb $t1,[$inp,#3] 253 ldrb $t1,[$inp,#3]
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/device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
ThumbDisassembler.c | 153 { "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1_B },
154 { "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
322 { "LDRB", 0xf8900000, 0xfff00000, LDM_REG_IMM12 }, // LDRB <rt>, [<rn>, {, #<imm12>]}
328 { "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label>
334 { "LDRB", 0xf8100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
[all...] |
/external/llvm/test/MC/ARM/ |
diagnostics.s | 560 ldrb r0, [r0, #1]! 561 ldrb r0, [r0, r1]! 562 ldrb r0, [r0], #1 563 ldrb r0, [r0], r1 605 @ CHECK-ERRORS: ldrb r0, [r0, #1]! 608 @ CHECK-ERRORS: ldrb r0, [r0, r1]! 611 @ CHECK-ERRORS: ldrb r0, [r0], #1 614 @ CHECK-ERRORS: ldrb r0, [r0], r1
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/external/v8/src/regexp/arm/ |
regexp-macro-assembler-arm.cc | 254 __ ldrb(r3, MemOperand(r0, char_size(), PostIndex)); 255 __ ldrb(r4, MemOperand(r2, char_size(), PostIndex)); 389 __ ldrb(r3, MemOperand(r0, char_size(), PostIndex)); 390 __ ldrb(r4, MemOperand(r2, char_size(), PostIndex)); 492 __ ldrb(r0, MemOperand(r0, r1)); 582 __ ldrb(r0, MemOperand(r0, current_character())); 596 __ ldrb(r0, MemOperand(r0, current_character())); [all...] |
/system/core/libpixelflinger/codeflinger/ |
ARMAssemblerProxy.cpp | 215 void ARMAssemblerProxy::LDRB(int cc, int Rd, int Rn, uint32_t offset) { 216 mTarget->LDRB(cc, Rd, Rn, offset);
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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
diagnostic.s | 66 ldrb w0, x1, x2, sxtx 201 ldst_single_wb_32 ldrb
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/bionic/libc/arch-arm64/denver64/bionic/ |
memcpy_base.S | 114 ldrb tmp1w, [src]
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/device/linaro/bootloader/arm-trusted-firmware/common/aarch32/ |
debug.S | 143 ldrb r0, [r4], #0x1
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/device/linaro/bootloader/arm-trusted-firmware/common/aarch64/ |
debug.S | 96 ldrb w0, [x4], #0x1
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/external/libavc/common/arm/ |
ih264_mem_fns_neon.s | 127 ldrb r3, [r1], #1
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/external/libavc/common/armv8/ |
ih264_intra_pred_chroma_av8.s | 463 ldrb w6, [x0], #1 465 ldrb w8, [x0], #1 466 ldrb w7, [x10], #1 467 ldrb w9, [x10], #1
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/external/libhevc/common/arm/ |
ihevc_mem_fns.s | 126 LDRB r3,[r1],#1
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ihevc_sao_edge_offset_class1_chroma.s | 109 LDRB r4,[r5,#2] @pu1_avail[2] 114 LDRB r4,[r5,#3] @pu1_avail[3] 132 LDRB r4,[r5,#2] @pu1_avail[2] 290 LDRB r4,[r5,#2] @pu1_avail[2]
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