| /external/llvm/test/MC/Disassembler/ARM/ |
| ldrd-armv4.txt | 9 # A8.6.68 LDRD (register)
13 # V5TE: ldrd
|
| /external/capstone/suite/MC/ARM/ |
| arm-memory-instructions.s.cs | 34 0xd0,0x20,0xc5,0xe1 = ldrd r2, r3, [r5]
35 0xdf,0x60,0xc2,0xe1 = ldrd r6, r7, [r2, #15]
36 0xd0,0x02,0xe9,0xe1 = ldrd r0, r1, [r9, #32]!
37 0xd8,0x60,0xc1,0xe0 = ldrd r6, r7, [r1], #8
38 0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0
39 0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0
40 0xd0,0x00,0x48,0xe0 = ldrd r0, r1, [r8], #-0
41 0xd3,0x40,0x81,0xe1 = ldrd r4, r5, [r1, r3]
42 0xd2,0x40,0xa7,0xe1 = ldrd r4, r5, [r7, r2]!
43 0xdc,0x00,0x88,0xe0 = ldrd r0, r1, [r8], r1
[all...] |
| /external/libopus/celt/arm/ |
| armopts.s.in | 28 ; (LDRD/STRD, etc., ARMv5E and later).
|
| armopts_gnu.s | 29 @ (LDRD/STRD, etc., ARMv5E and later).
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-ldm.ll | 9 ; CHECK: ldrd
10 ; CONSERVATIVE-NOT: ldrd
23 ; CONSERVATIVE-NOT: ldrd
37 ; CONSERVATIVE-NOT: ldrd
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| ldrd.ll | 12 ;V6: ldrd r2, r3, [r2]
|
| 2011-03-15-LdStMultipleBug.ll | 3 ; Do not form Thumb2 ldrd / strd if the offset is not multiple of 4.
13 ; CHECK-NOT: ldrd
|
| /bionic/libc/arch-arm/cortex-a15/bionic/ |
| strcmp.S | 65 /* Use LDRD whenever possible. */
86 use LDRD to load two words from each string in every loop iteration.
92 use LDRD to load two words from each string in every loop iteration, as in the fast path.
95 Use LDRD to load two words from every string in every loop iteration.
186 ldrd r2, r3, [r0], #8
187 ldrd r4, r5, [r1], #8
270 ldrd r2, r3, [r0], #8
272 ldrd r4, r5, [r1], #8
346 ldrd r6, r7, [sp]
347 ldrd r4, r5, [sp, #8
[all...] |
| /system/extras/tests/memtest/ |
| bandwidth.h | 178 const char *getName() { return "ldrd/strd"; }
181 // Copy using ldrd/strd instructions.
195 "ldrd r6, r7, [r0]\n"
197 "ldrd r6, r7, [r0, #8]\n"
199 "ldrd r6, r7, [r0, #16]\n"
201 "ldrd r6, r7, [r0, #24]\n"
203 "ldrd r6, r7, [r0, #32]\n"
205 "ldrd r6, r7, [r0, #40]\n"
207 "ldrd r6, r7, [r0, #48]\n"
209 "ldrd r6, r7, [r0, #56]\n
[all...] |
| /bionic/libc/arch-arm/cortex-a9/bionic/ |
| strcmp.S | 61 /* Use LDRD whenever possible. */
82 use LDRD to load two words from each string in every loop iteration.
88 use LDRD to load two words from each string in every loop iteration, as in the fast path.
91 Use LDRD to load two words from every string in every loop iteration.
182 ldrd r2, r3, [r0], #8
183 ldrd r4, r5, [r1], #8
266 ldrd r2, r3, [r0], #8
268 ldrd r4, r5, [r1], #8
328 ldrd r6, r7, [sp]
329 ldrd r4, r5, [sp, #8
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/epiphany/ |
| sample.d | 120 ae: 05e4 ldrd r0,\[r1,0x3\]
121 b0: 47ec 201f ldrd r10,\[r1,\+0xff\]
122 b4: 0561 ldrd r0,\[r1,r2\]
123 b6: 05e9 0080 ldrd r0,\[r1,\+fp\]
124 ba: 0d65 ldrd r0,\[r3\],r2
125 bc: 52ed 2480 ldrd r10,\[r12\],\+sp
|
| sample.s | 72 testmem ldrd
|
| allinsn.d | 351 00000308 \<ldrd\>:
362 328: 9269 2480 ldrd r12,\[r12,\+r12]
363 32c: 8de1 ldrd r4,\[r3,r3]
364 32e: 0061 ldrd r0,\[r0,r0]
365 330: cde9 2480 ldrd lr,\[fp,\+fp]
366 334: 16e9 4480 ldrd r16,\[sp,\+sp]
367 338: ca69 6080 ldrd r30,\[r2,\+r12]
368 33c: 0de9 0400 ldrd r0,\[fp,\+r3]
369 340: 9369 4480 ldrd r20,\[r12,\+lr]
372 344: 8de5 ldrd r4,\[r3],r
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| sp-pc-validations-bad.l | 25 [^:]*:44: Error: r15 not allowed here -- `ldrd r0,pc,\[r1,#4\]'
26 [^:]*:45: Error: r15 not allowed here -- `ldrd r0,pc,\[r1\],#4'
27 [^:]*:46: Error: r15 not allowed here -- `ldrd r0,pc,\[r1,#4\]!'
28 [^:]*:49: Error: r15 not allowed here -- `ldrd r0,pc,label'
29 [^:]*:50: Error: r15 not allowed here -- `ldrd r0,pc,\[PC,#-0\]'
30 [^:]*:53: Error: r15 not allowed here -- `ldrd r0,pc,\[r1,r2\]'
31 [^:]*:54: Error: r15 not allowed here -- `ldrd r0,pc,\[r1,r2\]!'
32 [^:]*:55: Error: r15 not allowed here -- `ldrd r0,pc,\[r1\],r2'
33 [^:]*:56: Error: cannot use register index with PC-relative addressing -- `ldrd r0,r1,\[r2,pc\]'
34 [^:]*:57: Error: cannot use register index with PC-relative addressing -- `ldrd r0,r1,\[r2,pc\]!
[all...] |
| ldst-pc.d | 13 0[0-9a-f]+ <[^>]+> e18f00d2 ldrd r0, \[pc, r2\]
|
| xscale.d | 26 0+40 <[^>]*> e1c100d0 ldrd r0, \[r1\]
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ |
| umoddi3.S | 24 ldrd r0, [sp, #8]
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| invalid-LDRD-arm.txt | 8 # A8.6.68 LDRD (register)
|
| /external/vixl/test/aarch32/ |
| test-assembler-aarch32.cc | 1182 // This load has a wider range than the Ldrd used below for the same
1187 // With the old pool manager, this Ldrd used to force pool emission before
1190 __ Ldrd(r2, r3, &l1);
1218 // This load has a wider range than the Ldrd used below for the same
1224 // Ldrd below should not need to rewind.
1230 __ Ldrd(r2, r3, &l1);
1277 // Ldrd below (if the pool is not already emitted due to the Ldr).
1283 // This load has a wider range than the Ldrd used below for the same
1288 // Generate nops, in order to bring the checkpoints of the Ldr and Ldrd
1300 __ Ldrd(eq, r2, r3, &l1)
[all...] |
| /external/llvm/test/MC/ARM/ |
| arm-memory-instructions.s | 115 @ LDRD (immediate)
117 ldrd r2, r3, [r5]
118 ldrd r6, r7, [r2, #15]
119 ldrd r0, r1, [r9, #32]!
120 ldrd r6, r7, [r1], #8
121 ldrd r0, r1, [r8], #0
122 ldrd r0, r1, [r8], #+0
123 ldrd r0, r1, [r8], #-0
125 @ CHECK: ldrd r2, r3, [r5] @ encoding: [0xd0,0x20,0xc5,0xe1]
126 @ CHECK: ldrd r6, r7, [r2, #15] @ encoding: [0xdf,0x60,0xc2,0xe1
[all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| diagnostics.s | 287 @ Out of order Rt/Rt2 operands for ldrd
288 ldrd r4, r3, [r8]
289 ldrd r4, r3, [r8, #8]!
290 ldrd r4, r3, [r8], #8
292 @ CHECK-ERRORS: ldrd r4, r3, [r8]
295 @ CHECK-ERRORS: ldrd r4, r3, [r8, #8]!
298 @ CHECK-ERRORS: ldrd r4, r3, [r8], #8
|
| arm-memory-instructions.s | 113 @ LDRD (immediate)
115 ldrd r3, r4, [r5]
116 ldrd r7, r8, [r2, #15]
117 ldrd r1, r2, [r9, #32]!
118 ldrd r6, r7, [r1], #8
119 ldrd r1, r2, [r8], #0
120 ldrd r1, r2, [r8], #+0
121 ldrd r1, r2, [r8], #-0
123 @ CHECK: ldrd r3, r4, [r5] @ encoding: [0xd0,0x30,0xc5,0xe1]
124 @ CHECK: ldrd r7, r8, [r2, #15] @ encoding: [0xdf,0x70,0xc2,0xe1
[all...] |
| /external/aac/libFDK/include/arm/ |
| scramble_arm.h | 112 #define USE_LDRD_STRD /* LDRD requires 8 byte data alignment. */
135 "ldrd r10, [%0, r5];\n" /* r10 = x[r5], x7 = x[r5+1] */
137 "ldrd r8, [%0, r6];\n" /* r8 = x[r6], r9 = x[r6+1]; */
|
| /external/vixl/doc/aarch32/design/ |
| literal-pool-aarch32.md | 15 For example, ldrd's range is [-1020, 1020] for 32bit T32 and [-255, 255] for
58 range (ldrd for example), that this will be hard to avoid.
70 ranges like ldrd and one other for bigger ranges.
|
| /art/runtime/arch/arm/ |
| instruction_set_features_arm.h | 68 // Are the ldrd and strd instructions atomic? This is commonly true when the Large Physical
|
