| /art/runtime/interpreter/mterp/mips64/ |
| op_sput_char.S | 1 %include "mips64/op_sput.S" {"helper":"MterpSetCharStatic"}
|
| op_sput_short.S | 1 %include "mips64/op_sput.S" {"helper":"MterpSetShortStatic"}
|
| op_add_double.S | 1 %include "mips64/fbinopWide.S" {"instr":"add.d f0, f0, f1"}
|
| op_add_double_2addr.S | 1 %include "mips64/fbinopWide2addr.S" {"instr":"add.d f0, f0, f1"}
|
| op_add_float.S | 1 %include "mips64/fbinop.S" {"instr":"add.s f0, f0, f1"}
|
| op_add_float_2addr.S | 1 %include "mips64/fbinop2addr.S" {"instr":"add.s f0, f0, f1"}
|
| op_add_int.S | 1 %include "mips64/binop.S" {"instr":"addu a0, a0, a1"}
|
| op_add_int_2addr.S | 1 %include "mips64/binop2addr.S" {"instr":"addu a0, a0, a1"}
|
| op_add_int_lit16.S | 1 %include "mips64/binopLit16.S" {"instr":"addu a0, a0, a1"}
|
| op_add_int_lit8.S | 1 %include "mips64/binopLit8.S" {"instr":"addu a0, a0, a1"}
|
| op_add_long.S | 1 %include "mips64/binopWide.S" {"instr":"daddu a0, a0, a1"}
|
| op_add_long_2addr.S | 1 %include "mips64/binopWide2addr.S" {"instr":"daddu a0, a0, a1"}
|
| op_aget_boolean.S | 1 %include "mips64/op_aget.S" { "load":"lbu", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
|
| op_aget_byte.S | 1 %include "mips64/op_aget.S" { "load":"lb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" }
|
| op_aget_char.S | 1 %include "mips64/op_aget.S" { "load":"lhu", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" }
|
| op_aget_short.S | 1 %include "mips64/op_aget.S" { "load":"lh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" }
|
| op_and_int.S | 1 %include "mips64/binop.S" {"instr":"and a0, a0, a1"}
|
| op_and_int_2addr.S | 1 %include "mips64/binop2addr.S" {"instr":"and a0, a0, a1"}
|
| op_and_int_lit16.S | 1 %include "mips64/binopLit16.S" {"instr":"and a0, a0, a1"}
|
| op_and_int_lit8.S | 1 %include "mips64/binopLit8.S" {"instr":"and a0, a0, a1"}
|
| op_and_long.S | 1 %include "mips64/binopWide.S" {"instr":"and a0, a0, a1"}
|
| op_and_long_2addr.S | 1 %include "mips64/binopWide2addr.S" {"instr":"and a0, a0, a1"}
|
| op_aput_boolean.S | 1 %include "mips64/op_aput.S" { "store":"sb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
|
| /art/runtime/arch/mips64/ |
| quick_method_frame_info_mips64.h | 28 namespace mips64 { namespace in namespace:art
31 (1 << art::mips64::RA);
33 (1 << art::mips64::S2) | (1 << art::mips64::S3) | (1 << art::mips64::S4) |
34 (1 << art::mips64::S5) | (1 << art::mips64::S6) | (1 << art::mips64::S7) |
35 (1 << art::mips64::GP) | (1 << art::mips64::S8)
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | 32 bool operator()(const mips64::GpuRegister& a, const mips64::GpuRegister& b) const {
37 class AssemblerMIPS64Test : public AssemblerTest<mips64::Mips64Assembler,
38 mips64::Mips64Label,
39 mips64::GpuRegister,
40 mips64::FpuRegister,
42 mips64::VectorRegister> {
44 typedef AssemblerTest<mips64::Mips64Assembler,
45 mips64::Mips64Label,
46 mips64::GpuRegister
[all...] |
