| /external/llvm/test/CodeGen/X86/ |
| sqrt-fastmath.ll | 16 ; NORECIP-NEXT: sqrtsd %xmm0, %xmm0
17 ; NORECIP-NEXT: retq
21 ; ESTIMATE-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
22 ; ESTIMATE-NEXT: retq
31 ; NORECIP-NEXT: sqrtss %xmm0, %xmm0
32 ; NORECIP-NEXT: retq
36 ; ESTIMATE-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
37 ; ESTIMATE-NEXT: vmulss %xmm1, %xmm0, %xmm2
38 ; ESTIMATE-NEXT: vmulss %xmm1, %xmm2, %xmm1
39 ; ESTIMATE-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm
[all...] |
| mfence.ll | 10 ; X32-NEXT: mfence
11 ; X32-NEXT: retl
15 ; X64-NEXT: mfence
16 ; X64-NEXT: retq
24 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
25 ; X32-NEXT: mfence
26 ; X32-NEXT: movl (%eax), %eax
27 ; X32-NEXT: retl
31 ; X64-NEXT: mfence
32 ; X64-NEXT: movl (%rdi), %ea
[all...] |
| widen_conv-2.ll | 10 ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
11 ; X86-NEXT: psllq $48, %xmm0
12 ; X86-NEXT: psrad $16, %xmm0
13 ; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
14 ; X86-NEXT: movq %xmm0, (%eax)
15 ; X86-NEXT: retl
19 ; X64-NEXT: psllq $48, %xmm0
20 ; X64-NEXT: psrad $16, %xmm0
21 ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
22 ; X64-NEXT: movq %xmm0, (%rdi
[all...] |
| avx512-bugfix-26264.ll | 7 ; AVX512BW-NEXT: vpsllw $7, %ymm0, %ymm0
8 ; AVX512BW-NEXT: vpmovb2m %zmm0, %k1
9 ; AVX512BW-NEXT: vmovupd (%rdi), %zmm1 {%k1}
10 ; AVX512BW-NEXT: kshiftrd $16, %k1, %k2
11 ; AVX512BW-NEXT: vmovupd 128(%rdi), %zmm3 {%k2}
12 ; AVX512BW-NEXT: kshiftrw $8, %k1, %k1
13 ; AVX512BW-NEXT: vmovupd 64(%rdi), %zmm2 {%k1}
14 ; AVX512BW-NEXT: kshiftrw $8, %k2, %k1
15 ; AVX512BW-NEXT: vmovupd 192(%rdi), %zmm4 {%k1}
16 ; AVX512BW-NEXT: vmovaps %zmm1, %zmm
[all...] |
| /external/mesa3d/src/util/ |
| list.h | 23 * next paragraph) shall be included in all copies or substantial portions
49 struct list_head *next; member in struct:list_head
55 item->next = item;
61 item->next = list->next;
62 list->next->prev = item;
63 list->next = item;
68 item->next = list;
70 list->prev->next = item;
82 to->next = from->next
[all...] |
| /external/llvm/test/MC/ARM/ |
| directive-eabi_attribute.s | 14 @ CHECK-OBJ-NEXT: TagName: conformance
15 @ CHECK-OBJ-NEXT: Value: 2.09
19 @ CHECK-OBJ-NEXT: TagName: CPU_raw_name
20 @ CHECK-OBJ-NEXT: Value: Cortex-A9
24 @ CHECK-OBJ-NEXT: TagName: CPU_name
25 @ CHECK-OBJ-NEXT: Value: cortex-a9
29 @ CHECK-OBJ-NEXT: Value: 10
30 @ CHECK-OBJ-NEXT: TagName: CPU_arch
31 @ CHECK-OBJ-NEXT: Description: ARM v7
35 @ CHECK-OBJ-NEXT: Value: 6
[all...] |
| /external/clang/test/OpenMP/ |
| distribute_dist_schedule_ast_print.cpp | 17 // CHECK-NEXT: #pragma omp distribute dist_schedule(static, 10)
19 // CHECK-NEXT: for (int i = 0; i < 2; ++i)
20 // CHECK-NEXT: a = 2;
22 // CHECK-NEXT: #pragma omp distribute dist_schedule(static, a)
24 // CHECK-NEXT: for (int i = 0; i < 2; ++i)
25 // CHECK-NEXT: a = 2;
31 // CHECK-NEXT: #pragma omp target
32 // CHECK-NEXT: #pragma omp teams
33 // CHECK-NEXT: #pragma omp distribute dist_schedule(static, 2)
34 // CHECK-NEXT: for (int i = 0; i < 10; ++i
[all...] |
| master_ast_print.cpp | 22 // CHECK-NEXT: #pragma omp parallel
23 // CHECK-NEXT: {
24 // CHECK-NEXT: #pragma omp master
25 // CHECK-NEXT: {
26 // CHECK-NEXT: a = 2;
27 // CHECK-NEXT: }
28 // CHECK-NEXT: }
|
| /external/llvm/test/CodeGen/Thumb2/ |
| segmented-stacks.ll | 16 ; Thumb-android-NEXT: mrc p15, #0, r4, c13, c0, #3
17 ; Thumb-android-NEXT: mov r5, sp
18 ; Thumb-android-NEXT: ldr r4, [r4, #252]
19 ; Thumb-android-NEXT: cmp r4, r5
20 ; Thumb-android-NEXT: blo .LBB0_2
23 ; Thumb-android-NEXT: mov r5, #0
24 ; Thumb-android-NEXT: push {lr}
25 ; Thumb-android-NEXT: bl __morestack
26 ; Thumb-android-NEXT: ldr lr, [sp], #4
27 ; Thumb-android-NEXT: pop {r4, r5
[all...] |
| /external/llvm/test/MC/ELF/ |
| debug-loc.s | 13 // CHECK-NEXT: Type: SHT_PROGBITS
14 // CHECK-NEXT: Flags [
15 // CHECK-NEXT: ]
16 // CHECK-NEXT: Address: 0x0
17 // CHECK-NEXT: Offset:
18 // CHECK-NEXT: Size: 61
19 // CHECK-NEXT: Link: 0
20 // CHECK-NEXT: Info: 0
21 // CHECK-NEXT: AddressAlignment: 1
22 // CHECK-NEXT: EntrySize:
[all...] |
| /external/llvm/test/MC/MachO/ |
| reloc-diff.s | 20 // CHECK-NEXT: Section __data {
21 // CHECK-NEXT: 0x10 0 2 n/a GENERIC_RELOC_LOCAL_SECTDIFF 1 0x0
22 // CHECK-NEXT: 0x0 0 2 n/a GENERIC_RELOC_PAIR 1 0x0
23 // CHECK-NEXT: 0x8 0 2 n/a GENERIC_RELOC_LOCAL_SECTDIFF 1 0x0
24 // CHECK-NEXT: 0x0 0 2 n/a GENERIC_RELOC_PAIR 1 0x0
25 // CHECK-NEXT: 0x4 0 2 n/a GENERIC_RELOC_LOCAL_SECTDIFF 1 0x0
26 // CHECK-NEXT: 0x0 0 2 n/a GENERIC_RELOC_PAIR 1 0x0
27 // CHECK-NEXT: 0x0 0 2 n/a GENERIC_RELOC_SECTDIFF 1 0x0
28 // CHECK-NEXT: 0x0 0 2 n/a GENERIC_RELOC_PAIR 1 0x0
29 // CHECK-NEXT:
[all...] |
| /external/llvm/test/MC/Mips/ |
| instr-analysis.s | 5 # CHECK-NEXT: 0: 0c 00 00 02 jal 8 <loc1>
6 # CHECK-NEXT: 4: 00 00 00 00 nop
9 # CHECK-NEXT: 8: 0c 00 00 06 jal 24 <loc3>
10 # CHECK-NEXT: c: 00 00 00 00 nop
13 # CHECK-NEXT: 10: 10 00 ff fd b -8 <loc1>
14 # CHECK-NEXT: 14: 00 00 00 00 nop
17 # CHECK-NEXT: 18: 10 43 ff fd beq $2, $3, -8 <loc2>
18 # CHECK-NEXT: 1c: 00 00 00 00 nop
19 # CHECK-NEXT: 20: 04 11 ff f9 bal -24 <loc1>
20 # CHECK-NEXT: 24: 00 00 00 00 no
[all...] |
| /external/llvm/test/Object/AArch64/ |
| yaml2obj-elf-aarch64-rel.yaml | 5 # CHECK-NEXT: Type: SHT_RELA
6 # CHECK-NEXT: Link: .symtab
7 # CHECK-NEXT: AddressAlign: 0x0000000000000008
8 # CHECK-NEXT: Info: .text
9 # CHECK-NEXT: Relocations:
10 # CHECK-NEXT: - Offset: 0x0000000000000000
11 # CHECK-NEXT: Symbol: main
12 # CHECK-NEXT: Type: R_AARCH64_ABS64
13 # CHECK-NEXT: - Offset: 0x0000000000000008
14 # CHECK-NEXT: Symbol: mai
[all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ELF/ |
| debug-loc.s | 11 // CHECK-NEXT: (('sh_name', 0x00000011) # '.debug_line'
12 // CHECK-NEXT: ('sh_type', 0x00000001)
13 // CHECK-NEXT: ('sh_flags', 0x0000000000000000)
14 // CHECK-NEXT: ('sh_addr', 0x0000000000000000)
15 // CHECK-NEXT: ('sh_offset', 0x0000000000000044)
16 // CHECK-NEXT: ('sh_size', 0x000000000000003d)
17 // CHECK-NEXT: ('sh_link', 0x00000000)
18 // CHECK-NEXT: ('sh_info', 0x00000000)
19 // CHECK-NEXT: ('sh_addralign', 0x0000000000000001)
20 // CHECK-NEXT: ('sh_entsize', 0x0000000000000000
[all...] |
| /external/swiftshader/third_party/subzero/tests_lit/asan_tests/ |
| instrumentlocals.ll | 31 ; DUMP-NEXT: define internal void @func() {
32 ; DUMP-NEXT: __0:
33 ; DUMP-NEXT: %__$rz0 = alloca i8, i32 32, align 8
34 ; DUMP-NEXT: %local1 = alloca i8, i32 64, align 8
35 ; DUMP-NEXT: %local2 = alloca i8, i32 64, align 8
36 ; DUMP-NEXT: %local3 = alloca i8, i32 64, align 8
37 ; DUMP-NEXT: %local4 = alloca i8, i32 128, align 8
38 ; DUMP-NEXT: %local5 = alloca i8, i32 96, align 8
39 ; DUMP-NEXT: %shadowIndex = lshr i32 %__$rz0, 3
40 ; DUMP-NEXT: %firstShadowLoc = add i32 %shadowIndex, 53687091
[all...] |
| /external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/ |
| and.ll | 29 ; ASM-NEXT:.LAnd1WithR0$__0:
30 ; ASM-NEXT: and r0, r0, #1
33 ; DIS-NEXT: 0: e2000001
36 ; IASM-NEXT:.LAnd1WithR0$__0:
37 ; IASM-NEXT: .byte 0x1
38 ; IASM-NEXT: .byte 0x0
39 ; IASM-NEXT: .byte 0x0
40 ; IASM-NEXT: .byte 0xe2
48 ; ASM-NEXT:.LAnd2Regs$__0:
49 ; ASM-NEXT: and r0, r0, r
[all...] |
| eor.ll | 29 ; ASM-NEXT:.LEor1WithR0$__0:
30 ; ASM-NEXT: eor r0, r0, #1
33 ; DIS-NEXT: 0: e2200001
36 ; IASM-NEXT:.LEor1WithR0$__0:
37 ; IASM-NEXT: .byte 0x1
38 ; IASM-NEXT: .byte 0x0
39 ; IASM-NEXT: .byte 0x20
40 ; IASM-NEXT: .byte 0xe2
48 ; ASM-NEXT:.LEor2Regs$__0:
49 ; ASM-NEXT: eor r0, r0, r
[all...] |
| orr.ll | 29 ; ASM-NEXT:.LOr1WithR0$__0:
30 ; ASM-NEXT: orr r0, r0, #1
33 ; DIS-NEXT: 0: e3800001
36 ; IASM-NEXT:.LOr1WithR0$__0:
37 ; IASM-NEXT: .byte 0x1
38 ; IASM-NEXT: .byte 0x0
39 ; IASM-NEXT: .byte 0x80
40 ; IASM-NEXT: .byte 0xe3
48 ; ASM-NEXT:.LOr2Regs$__0:
49 ; ASM-NEXT: orr r0, r0, r
[all...] |
| /external/clang/test/CodeGenObjC/ |
| arc-ternary-op.m | 8 // CHECK-NEXT: [[X:%.*]] = alloca i8*,
9 // CHECK-NEXT: [[RELVAL:%.*]] = alloca i8*
10 // CHECK-NEXT: [[RELCOND:%.*]] = alloca i1
11 // CHECK-NEXT: zext
12 // CHECK-NEXT: store
13 // CHECK-NEXT: [[XPTR1:%.*]] = bitcast i8** [[X]] to i8*
14 // CHECK-NEXT: call void @llvm.lifetime.start(i64 8, i8* [[XPTR1]])
15 // CHECK-NEXT: [[T0:%.*]] = load i8, i8* [[COND]]
16 // CHECK-NEXT: [[T1:%.*]] = trunc i8 [[T0]] to i1
17 // CHECK-NEXT: store i1 false, i1* [[RELCOND]
[all...] |
| arc-loadweakretained-release.m | 32 // CHECK-NEXT: [[SEVENTEEN:%.*]] = bitcast i8* [[SIXTEEN]] to {{%.*}}
33 // CHECK-NEXT: [[EIGHTEEN:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_.6
34 // CHECK-NEXT: [[NINETEEN:%.*]] = bitcast %0* [[SEVENTEEN]] to i8*
35 // CHECK-NEXT: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend
36 // CHECK-NEXT: [[TWENTY:%.*]] = bitcast %0* [[SEVENTEEN]] to i8*
37 // CHECK-NEXT: call void @objc_release(i8* [[TWENTY]])
47 // CHECK-NEXT: [[WEAK:%.*]] = alloca i8*
48 // CHECK-NEXT: [[INCRTEMP:%.*]] = alloca i8*
49 // CHECK-NEXT: [[CONDCLEANUPSAVE:%.*]] = alloca i8*
50 // CHECK-NEXT: [[CONDCLEANUP:%.*]] = alloca i
[all...] |
| /external/clang/test/CodeGenCXX/ |
| function-template-specialization.cpp | 7 T* next(T* ptr, const U& diff);
10 T* next(T* ptr, const U& diff) { function
16 iptr = next(iptr, diff);
19 fptr = next(fptr, diff);
23 T* next(T* ptr, const U& diff);
26 iptr = next(iptr, diff);
29 dptr = next(dptr, diff);
|
| /external/clang/test/CoverageMapping/ |
| macroception.c | 9 // CHECK-NEXT: Expansion,File 0, [[@LINE+2]]:12 -> [[@LINE+2]]:14 = #0
10 // CHECK-NEXT: File 0, [[@LINE+1]]:14 -> [[@LINE+3]]:2 = #0
14 // CHECK-NEXT: File 1, 4:12 -> 4:14 = #0
15 // CHECK-NEXT: Expansion,File 1, 4:12 -> 4:14 = #0
16 // CHECK-NEXT: File 2, 3:12 -> 3:13 = #0
19 // CHECK-NEXT: File 0, [[@LINE+2]]:14 -> [[@LINE+4]]:4 = #0
20 // CHECK-NEXT: Expansion,File 0, [[@LINE+3]]:1 -> [[@LINE+3]]:4 = #0
24 // CHECK-NEXT: File 1, 6:13 -> 6:16 = #0
25 // CHECK-NEXT: Expansion,File 1, 6:13 -> 6:16 = #0
26 // CHECK-NEXT: File 2, 5:13 -> 5:14 = #
[all...] |
| /external/libcxx/test/std/containers/associative/map/map.modifiers/ |
| erase_key.pass.cpp | 45 assert(next(m.begin())->first == 2);
46 assert(next(m.begin())->second == 2.5);
47 assert(next(m.begin(), 2)->first == 3);
48 assert(next(m.begin(), 2)->second == 3.5);
49 assert(next(m.begin(), 3)->first == 4);
50 assert(next(m.begin(), 3)->second == 4.5);
51 assert(next(m.begin(), 4)->first == 5);
52 assert(next(m.begin(), 4)->second == 5.5);
53 assert(next(m.begin(), 5)->first == 6);
54 assert(next(m.begin(), 5)->second == 6.5)
[all...] |
| /external/libcxx/test/std/containers/associative/map/map.ops/ |
| lower_bound.pass.cpp | 47 assert(r == next(m.begin()));
49 assert(r == next(m.begin(), 2));
51 assert(r == next(m.begin(), 3));
53 assert(r == next(m.begin(), 4));
55 assert(r == next(m.begin(), 5));
57 assert(r == next(m.begin(), 6));
59 assert(r == next(m.begin(), 7));
61 assert(r == next(m.begin(), 0));
63 assert(r == next(m.begin(), 1));
65 assert(r == next(m.begin(), 2))
[all...] |
| /external/llvm/test/MC/AArch64/ |
| elf-reloc-pcreladdressing.s | 11 // OBJ-NEXT: Section {{.*}} .rela.text {
12 // OBJ-NEXT: 0x0 R_AARCH64_ADR_PREL_LO21 some_label 0x0
13 // OBJ-NEXT: 0x4 R_AARCH64_ADR_PREL_PG_HI21 some_label 0x0
14 // OBJ-NEXT: 0x8 R_AARCH64_ADR_GOT_PAGE some_label 0x0
15 // OBJ-NEXT: 0xC R_AARCH64_LD64_GOT_LO12_NC some_label 0x0
16 // OBJ-NEXT: }
17 // OBJ-NEXT: ]
|
