| /device/linaro/bootloader/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ |
| div.asm | 52 ORRS r12, r0, r1
|
| udivmoddi4.S | 26 orrs r2, r2, r3
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| armv1.d | 28 0+44 <[^>]*> e1900000 ? orrs r0, r0, r0
|
| thumb32.s | 153 arit3 orr orrs orr.w orrs.w
|
| thumb-eabi.d | 38 0+038 <[^>]+> 4318 orrs r0, r3
|
| thumb.d | 39 0+038 <[^>]+> 4318 orrs r0, r3
|
| thumb32.d | 169 0[0-9a-f]+ <[^>]+> 4300 orrs r0, r0
170 0[0-9a-f]+ <[^>]+> 4305 orrs r5, r0
171 0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5
172 0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5
173 0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5
179 0[0-9a-f]+ <[^>]+> ea50 0000 orrs\.w r0, r0, r0
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| select_xform.ll | 298 ; T2: orrs r0, {{r[0-9]+}}
313 ; T2: orrs r0, {{r[0-9]+}}
|
| shifter_operand.ll | 72 ; CHECk-THUMB: orrs r0, r1
|
| atomic-64bit.ll | 180 ; CHECK: orrs {{r[0-9]+}}, [[MISMATCH_LO]], [[MISMATCH_HI]]
194 ; CHECK-THUMB-LE: orrs.w {{.*}}, [[MISMATCH_LO]], [[MISMATCH_HI]]
|
| atomic-ops-v8.ll | [all...] |
| /external/valgrind/docs/internals/ |
| t-chaining-notes.txt | 54 arm codegen: Generate ORRS for CmpwNEZ32(Or32(x,y))
|
| /art/compiler/optimizing/ |
| scheduler_arm.cc | 222 // Orrs
365 // Orrs, IT, Mov
[all...] |
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| loopfilter_16_neon.asm | 449 orrs r5, r5, r6 ; Check for 0
502 orrs r5, r5, r6 ; Check for 0
|
| /external/vixl/src/aarch32/ |
| constants-aarch32.cc | 218 return "orrs";
|
| assembler-aarch32.h | 2717 void orrs(Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
2720 void orrs(Condition cond, Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
2723 void orrs(EncodingSize size, function in class:vixl::aarch32::Assembler
[all...] |
| /prebuilts/vndk/v27/arm/arch-arm-armv7-a-neon/shared/vndk-core/ |
| libvixl-arm.so | |
| /prebuilts/vndk/v27/arm64/arch-arm-armv7-a-neon/shared/vndk-core/ |
| libvixl-arm.so | |
| /art/test/570-checker-select/src/ |
| Main.java | 419 /// CHECK-NEXT: orrs ip, {{r\d+}}, {{r\d+}}
429 /// CHECK-NEXT: orrs ip, {{r\d+}}, {{r\d+}}
[all...] |
| /external/vixl/test/aarch32/ |
| test-disasm-a32.cc | 426 "orrs r0, ip\n");
431 COMPARE_BOTH(Orns(r0, r1, 0x00ffffff), "orrs r0, r1, #0xff000000\n");
437 "orrs r0, r1, r0\n");
473 "orrs r0, ip\n");
487 "orrs r0, ip\n");
[all...] |
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| 64bit.pnacl.ll | 450 ; ARM32: orrs {{r.*}}, {{r.*}}
474 ; ARM32-NOT: orrs
495 ; ARM32: orrs {{r.*}}, {{r.*}}
514 ; ARM32: orrs {{r.*}}, {{r.*}}
533 ; ARM32: orrs {{r.*}}, {{r.*}}
[all...] |
| /art/runtime/interpreter/mterp/out/ |
| mterp_arm.S | [all...] |
| /prebuilts/vndk/v27/x86/arch-x86-x86/shared/vndk-core/ |
| libvixl-arm.so | |
| /prebuilts/vndk/v27/x86_64/arch-x86-x86_64/shared/vndk-core/ |
| libvixl-arm.so | |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeARM_T2_32.c | 139 #define ORRS 0x4300
764 return push_inst16(compiler, ORRS | RD3(dst) | RN3(arg2));
[all...] |
