| /frameworks/compile/mclinker/lib/Core/ |
| IRBuilder.cpp | 389 uint64_t IRBuilder::AppendEhFrame(EhFrame::CIE& pCIE, EhFrame& pEhFrame) {
390 pEhFrame.addCIE(pCIE);
391 pEhFrame.getSection().setSize(pEhFrame.getSection().size() + pCIE.size());
392 return pCIE.size();
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/ |
| PcieInitLib.c | 875 //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE
[all...] |
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/ |
| AcpiSmmPlatform.c | 714 // Enable bit13 (EGPE), 14 (GPIO) ,17 (PCIE) in GPE0_EN
737 // Enable bit13 (EGPE), 14 (GPIO) ,17 (PCIE) in GPE0_EN
763 // Enable bit13 (EGPE), 14 (GPIO), 17 (PCIE) in GPE0_EN
[all...] |
| /external/kernel-headers/original/uapi/linux/ |
| pci_regs.h | 28 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
474 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
475 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
620 * are only present on devices with PCIe Capability version 2.
[all...] |
| /external/syslinux/gpxe/src/drivers/net/ |
| atl1e.c | 705 DBG("atl1e: configure failed, PCIE phy link down\n");
866 /* check if PCIE PHY Link down */
[all...] |
| sky2.h | 116 P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */
121 P_REL_PCIE_RESET_ASS = 1<<21, /* PCIe Reset Asserted */
123 P_REL_PCIE_EXIT_L1_ST = 1<<19, /* PCIe Exit L1 State */
125 P_REL_PCIE_RX_EX_IDLE = 1<<17, /* PCIe Rx Exit Electrical Idle State */
129 P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */
134 P_GAT_PCIE_RESET_ASS = 1<<5, /* PCIe Reset Asserted */
136 P_GAT_PCIE_ENTER_L1_ST = 1<<3, /* PCIe Enter L1 State */
138 P_GAT_PCIE_RX_EL_IDLE = 1<<1, /* PCIe Rx Electrical Idle State */
153 P_CF1_DIS_REL_EVT_RST = 1<<24, /* Dis. Rel. Event during PCIE reset */
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/ |
| if_mskreg.h | 2 * Defines and macros for the PCIe Marvell Yukon gigabit ethernet adapter product family
354 #define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */
359 #define PCI_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */
361 #define PCI_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */
363 #define PCI_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */
366 #define PCI_GAT_PCIE_RST_ASSERTED BIT_10 /* PCIe Reset Asserted */
371 #define PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */
373 #define PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */
375 #define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */
379 #define PCI_CF1_DIS_REL_EVT_RST BIT_24 /* Dis. Rel. Event during PCIE reset */
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/ |
| D03Mbig.asl | 17 // Mbi-gen pcie subsys
|
| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/SataSiI3132Dxe/ |
| SataSiI3132.c | 2 * PCIe Sata support for the Silicon Image I3132
|
| /device/linaro/bootloader/edk2/OvmfPkg/PciHotPlugInitDxe/ |
| PciHotPlugInit.c | 3 driver with resource padding information, for PCIe hotplug purposes.
|
| /device/linaro/bootloader/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/ |
| Pci.h | 62 // PCIE device/port types
|
| Pci.c | [all...] |
| /external/autotest/client/site_tests/network_EthCaps/ |
| network_EthCaps.py | 229 # In fact, WoL only known to work for PCIe Ethernet devices.
|
| /external/f2fs-tools/tools/sg_write_buffer/ |
| sg_lib_data.c | [all...] |
| /external/mesa3d/src/mesa/drivers/dri/common/xmlpool/ |
| t_options.h | 307 DRI_CONF_ENUM(2,gettext("Only GART (AGP/PCIE) memory (if available)")) \
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/ |
| D05Iort.asl | 269 /* mbi-gen1 pcie, named component */
300 /* mbi-gen1 pcie, named component */
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/CelloBoard/ |
| CelloBoard.dsc | 411 # PCIe Support
447 # PCIe Configuration: x4x2x2
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Overdrive1000Board/ |
| Overdrive1000Board.dsc | 416 # PCIe Support
464 # PCIe Configuration: x4x2x2 (=2 See Include/FDKGionb.h)
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/ |
| OverdriveBoard.dsc | 418 # PCIe Support
483 # PCIe Configuration: x4x4
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/D05/ |
| D05.dsc | 170 ## enable all the pcie device, because it is ok for bios
619 #PCIe Support
|
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/ |
| PlatformEarlyInit.c | 563 // Do Early PCIe init.
565 DEBUG ((EFI_D_INFO, "Early PCIe controller initialization\n"));
[all...] |
| /frameworks/compile/mclinker/include/mcld/ |
| IRBuilder.h | 351 /// @param [in, out] pCIE The appended CIE entry.
354 static uint64_t AppendEhFrame(EhFrame::CIE& pCIE, EhFrame& pEhFrame);
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/ |
| VfrStrings.uni | 450 #string STR_PCI_STRING #language en-US "PCIe"
[all...] |
| /device/google/marlin/ |
| WCNSS_qcom_cfg.ini | 277 # Enabling this feature will put target wow and shutdown pcie link
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/D03/ |
| D03.dsc | 488 #PCIe Support
|
