| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/ |
| SlotConfig.c | 62 // Hide mini PCIe slots per SKU
|
| /external/kernel-headers/original/uapi/linux/ |
| switchtec_ioctl.h | 3 * Microsemi Switchtec PCIe Driver
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/ |
| AddSmbiosType9.c | 75 DEBUG((EFI_D_ERROR,"PCIe device plot in slot Seg %d bdf %d %d %d\r\n",SegmentNumber,BusNumber,DeviceNumber,FunctionNumber));
154 SlotDesignationStrLen = UnicodeSPrint (SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE Slot%d", Type9Record->SlotID);
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/ARM/Juno/AcpiTables/ |
| AcpiSsdtRootPci.asl | 194 If(And(CTRL,0x10)) { // OS restoring PCIe cap structure?
195 // Set status to not restore PCIe cap structure
|
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ |
| PciHostBridge.asi | 163 // Bus 0, Device 23 - PCIe port 0
190 // Bus 0, Device 23 - PCIe port 0
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/ |
| PciExpress.c | 336 // Parse thro all the functions of the endpoint and find the PCIe Cap ID (offset 10h) and if
341 // Find the PCIe Cap Id (offset 10h)
365 // Find the PCIe Cap Id (offset 10h)
560 @param[in] RootPortConfig Pointer to the given pcie root port configuration
561 @param[in] PciExpressBar Base address of pcie space
690 // Enable the PCIe CLKREQ#
780 // PCIe Hot Plug SCI Enable
882 // Set up the Posted and Non Posted Request sizes for PCIe
|
| /external/tensorflow/tensorflow/core/common_runtime/gpu/ |
| process_state.h | 106 // should be 0. On machines with multiple PCIe buses, it should be
107 // the index of one of the PCIe buses. If the bus_id is invalid,
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/ |
| PcieInitLib.c | 32 #define PCIE_GEN1 0 /* PCIE 1.0 */
33 #define PCIE_GEN2 1 /* PCIE 2.0 */
34 #define PCIE_GEN3 2 /* PCIE 3.0 */
838 /* Configure vmid/asid table in PCIe host */
866 * init vmid and asid tables for all PCIe devices as 0
[all...] |
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/ |
| GloblNvs.asl | 115 Offset(117), // PCIe Dock:
160 OSCC, 8, // (225) PCIE OSC Control
161 NEXP, 8, // (226) Native PCIE Setup Value
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/ |
| Iscp.h | 195 /// ISCP PCIE Reset structure
197 UINT32 Version; ///< Version of PCIE reset Buffer structure
336 #define PCIE_SIG (0x45494350) //"PCIE" spelled backwards - PCIE Reset
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/ |
| RuntimeAccess.c | 144 // PCIe memory base.
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/ |
| MultiPlatformLib.c | 87 // Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base.
|
| /external/syslinux/gpxe/src/drivers/net/ |
| myri10ge_mcp.h | 403 throttle_factor = 256 * pcie-raw-speed / tx_speed
404 tx_speed = 256 * pcie-raw-speed / throttle_factor
406 For PCI-E x8: pcie-raw-speed == 16Gb/s
407 For PCI-E x4: pcie-raw-speed == 8Gb/s
|
| /device/google/marlin/sepolicy/ |
| genfs_contexts | 41 genfscon sysfs /devices/soc/600000.qcom,pcie u:object_r:sysfs_pcie:s0
50 genfscon sysfs /devices/soc/600000.qcom,pcie/pci0000:00/0000:00:00.0/0000:01:00.0/net/wlan0 u:object_r:sysfs_net:s0
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/ |
| Iort.asl | 57 /* ITS 3, pcie */
161 /* mbi-gen pcie, named component */
|
| /device/linaro/bootloader/arm-trusted-firmware/docs/plat/ |
| poplar.rst | 20 PCIE One PCIe 2.0 interfaces
|
| /device/linaro/bootloader/edk2/SecurityPkg/Tcg/Opal/OpalPasswordSmm/ |
| OpalPasswordSmm.c | 226 @retval - PCIE base address of this RootPort
256 // Skip PCIe Command & Status registers
273 Configure RootPort for downstream PCIe NAND devices.
275 @param[in] RpBase - PCIe configuration space address of this RootPort
301 /// Configue PCIE configuration space for RootPort
367 /// Configure RootPort for PCIe AHCI/NVME devices.
383 /// Enable PCIE decode for RootPort
[all...] |
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| PchRegsPcu.h | [all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ |
| ComPhyCp110.c | 47 * PIPE selector include USB and PCIe options.
205 /* Set PHY mode to PCIe */
212 * for 0x7 only if the PCIe clock is output
232 /* Select bits for PCIE Gen3(32bit) */
987 UINT32 PcieBy4 = 1; // Indicating if first 4 lanes set to PCIE
[all...] |
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/ |
| PciHostBridgeResourceAllocation.c | 2 * Implementation of the Pci Host Bridge Resource Allocation for the Xpress-RICH3 PCIe Root Complex
608 // Is PCIe capability ?
610 // Get PCIe Device Capabilities
|
| /external/ltp/testcases/kernel/device-drivers/pci/tpci_kernel/ |
| ltp_tpci.c | 555 /* skip the test if device doesn't have PCIe capability */
570 prk_info("correct val read using PCIE driver installed: 0x%x",
575 prk_err("incorrect val read. PCIE driver/device not installed: 0x%x",
|
| /device/google/marlin/ |
| ueventd.common.rc | 220 /sys/devices/soc/600000.qcom,pcie/pci0000:00/0000:00:00.0/0000:01:00.0/net/wlan0/queues/rx-* rps_cpus 0660 system system
221 /sys/devices/soc/600000.qcom,pcie/pci0000:00/0000:00:00.0/0000:01:00.0/net/p2p0/queues/rx-* rps_cpus 0660 system system
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Ppi/ |
| IscpPpi.h | 161 /// ISCP PCIE Reset Transaction
166 IN OUT ISCP_PCIE_RESET_INFO *PcieResetInfo ///< Pointer to PCIE Reset info structure
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/ |
| QNCInit.c | 243 // Initialize PCIE root ports
486 // Report unused PCIe config space as reserved.
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformSmm/ |
| S3Save.c | 121 //Bus , Dev, Func, PCIE device
131 //Bus , Dev, Func, PCIE device
|
