| /device/linaro/bootloader/edk2/MdePkg/Library/BaseCpuLib/Ipf/ |
| CpuFlushTlb.s | 36 extr.u r14 = r10, 32, 32 // r14 <- count1
39 extr.u r10 = r10, 0, 32 // r10 <- count2
40 add r10 = -1, r10
44 mov ar.lc = r10 // LC <- count2
|
| /prebuilts/go/darwin-x86/src/crypto/sha512/ |
| sha512block_amd64.s | 158 MOVQ (2*8)(BP), R10 // c = H2
168 SHA512ROUND0(0, 0x428a2f98d728ae22, R8, R9, R10, R11, R12, R13, R14, R15)
169 SHA512ROUND0(1, 0x7137449123ef65cd, R15, R8, R9, R10, R11, R12, R13, R14)
170 SHA512ROUND0(2, 0xb5c0fbcfec4d3b2f, R14, R15, R8, R9, R10, R11, R12, R13)
171 SHA512ROUND0(3, 0xe9b5dba58189dbbc, R13, R14, R15, R8, R9, R10, R11, R12)
172 SHA512ROUND0(4, 0x3956c25bf348b538, R12, R13, R14, R15, R8, R9, R10, R11)
173 SHA512ROUND0(5, 0x59f111f1b605d019, R11, R12, R13, R14, R15, R8, R9, R10)
174 SHA512ROUND0(6, 0x923f82a4af194f9b, R10, R11, R12, R13, R14, R15, R8, R9)
175 SHA512ROUND0(7, 0xab1c5ed5da6d8118, R9, R10, R11, R12, R13, R14, R15, R8)
176 SHA512ROUND0(8, 0xd807aa98a3030242, R8, R9, R10, R11, R12, R13, R14, R15
[all...] |
| /prebuilts/go/linux-x86/src/crypto/sha512/ |
| sha512block_amd64.s | 158 MOVQ (2*8)(BP), R10 // c = H2
168 SHA512ROUND0(0, 0x428a2f98d728ae22, R8, R9, R10, R11, R12, R13, R14, R15)
169 SHA512ROUND0(1, 0x7137449123ef65cd, R15, R8, R9, R10, R11, R12, R13, R14)
170 SHA512ROUND0(2, 0xb5c0fbcfec4d3b2f, R14, R15, R8, R9, R10, R11, R12, R13)
171 SHA512ROUND0(3, 0xe9b5dba58189dbbc, R13, R14, R15, R8, R9, R10, R11, R12)
172 SHA512ROUND0(4, 0x3956c25bf348b538, R12, R13, R14, R15, R8, R9, R10, R11)
173 SHA512ROUND0(5, 0x59f111f1b605d019, R11, R12, R13, R14, R15, R8, R9, R10)
174 SHA512ROUND0(6, 0x923f82a4af194f9b, R10, R11, R12, R13, R14, R15, R8, R9)
175 SHA512ROUND0(7, 0xab1c5ed5da6d8118, R9, R10, R11, R12, R13, R14, R15, R8)
176 SHA512ROUND0(8, 0xd807aa98a3030242, R8, R9, R10, R11, R12, R13, R14, R15
[all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 121 {{al, r7, r8, r10, ROR, 21},
124 "al r7 r8 r10 ROR 21",
131 {{al, r14, r13, r10, LSL, 22},
134 "al r14 r13 r10 LSL 22",
136 {{al, r9, r10, r11, ROR, 2},
139 "al r9 r10 r11 ROR 2",
206 {{al, r7, r10, r10, ROR, 19},
209 "al r7 r10 r10 ROR 19"
[all...] |
| test-assembler-cond-rd-rn-operand-rm-t32.cc | 130 {{al, r3, r4, r10}, false, al, "al r3 r4 r10", "al_r3_r4_r10"},
140 {{al, r10, r6, r7}, false, al, "al r10 r6 r7", "al_r10_r6_r7"},
143 {{al, r5, r10, r6}, false, al, "al r5 r10 r6", "al_r5_r10_r6"},
149 {{al, r6, r2, r10}, false, al, "al r6 r2 r10", "al_r6_r2_r10"},
151 {{al, r3, r10, r1}, false, al, "al r3 r10 r1", "al_r3_r10_r1"}
[all...] |
| test-assembler-cond-rd-operand-rn-in-it-block-t32.cc | 106 {{eq, r0, r10}, true, eq, "eq r0 r10", "eq_r0_r10"},
121 {{eq, r1, r10}, true, eq, "eq r1 r10", "eq_r1_r10"},
136 {{eq, r2, r10}, true, eq, "eq r2 r10", "eq_r2_r10"},
151 {{eq, r3, r10}, true, eq, "eq r3 r10", "eq_r3_r10"},
166 {{eq, r4, r10}, true, eq, "eq r4 r10", "eq_r4_r10"}
[all...] |
| test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc | 127 {{gt, r1, r7, r10, ROR, 16},
130 "gt r1 r7 r10 ROR 16",
202 {{al, r4, r10, r4, ROR, 8},
205 "al r4 r10 r4 ROR 8",
242 {{hi, r10, r2, r2, ROR, 16},
245 "hi r10 r2 r2 ROR 16",
267 {{ne, r4, r7, r10, ROR, 16},
270 "ne r4 r7 r10 ROR 16",
327 {{le, r0, r10, r9, ROR, 0},
330 "le r0 r10 r9 ROR 0"
[all...] |
| test-assembler-cond-rd-rn-rm-t32.cc | 154 {{al, r1, r2, r10}, false, al, "al r1 r2 r10", "al_r1_r2_r10"},
157 {{al, r6, r9, r10}, false, al, "al r6 r9 r10", "al_r6_r9_r10"},
165 {{al, r10, r3, r13}, false, al, "al r10 r3 r13", "al_r10_r3_r13"},
166 {{al, r10, r10, r2}, false, al, "al r10 r10 r2", "al_r10_r10_r2"}
[all...] |
| test-assembler-cond-rd-rn-operand-rm-a32.cc | 130 {{ge, r5, r11, r10}, false, al, "ge r5 r11 r10", "ge_r5_r11_r10"},
133 {{eq, r1, r10, r13}, false, al, "eq r1 r10 r13", "eq_r1_r10_r13"},
139 {{le, r3, r9, r10}, false, al, "le r3 r9 r10", "le_r3_r9_r10"},
143 {{eq, r9, r14, r10}, false, al, "eq r9 r14 r10", "eq_r9_r14_r10"},
150 {{vc, r10, r8, r14}, false, al, "vc r10 r8 r14", "vc_r10_r8_r14"}
[all...] |
| test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc | 112 {{al, r9, r10, r5, ROR, 16},
115 "al r9 r10 r5 ROR 16",
152 {{al, r10, r14, r10, ROR, 24},
155 "al r10 r14 r10 ROR 24",
157 {{al, r10, r1, r6, ROR, 8},
160 "al r10 r1 r6 ROR 8",
162 {{al, r1, r11, r10, ROR, 0},
165 "al r1 r11 r10 ROR 0"
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 116 const TestData kTests[] = {{{al, r11, r13, r10, ASR, 9},
119 "al r11 r13 r10 ASR 9",
131 {{al, r14, r6, r10, LSR, 32},
134 "al r14 r6 r10 LSR 32",
156 {{al, r10, r12, r4, ASR, 2},
159 "al r10 r12 r4 ASR 2",
161 {{al, r6, r10, r0, LSR, 8},
164 "al r6 r10 r0 LSR 8",
176 {{al, r2, r10, r11, ASR, 1},
179 "al r2 r10 r11 ASR 1"
[all...] |
| /external/libffi/src/tile/ |
| tile.S | 83 #define FRAME_SIZE r10
231 On entry, lr points to the closure plus 8 bytes, and r10
252 /* Save return address (in r10 due to closure stub wrapper). */
253 SW sp, r10
254 .cfi_return_column r10
255 .cfi_offset r10, 0
258 addli r10, sp, -(CLOSURE_FRAME_SIZE - REG_SIZE)
262 SW r10, sp
271 addi r10, sp, LINKAGE_SIZE
275 STORE_REG(r0, r10)
[all...] |
| /external/python/cpython2/Modules/_ctypes/libffi/src/tile/ |
| tile.S | 83 #define FRAME_SIZE r10
231 On entry, lr points to the closure plus 8 bytes, and r10
252 /* Save return address (in r10 due to closure stub wrapper). */
253 SW sp, r10
254 .cfi_return_column r10
255 .cfi_offset r10, 0
258 addli r10, sp, -(CLOSURE_FRAME_SIZE - REG_SIZE)
262 SW r10, sp
271 addi r10, sp, LINKAGE_SIZE
275 STORE_REG(r0, r10)
[all...] |
| /external/python/cpython3/Modules/_ctypes/libffi/src/tile/ |
| tile.S | 83 #define FRAME_SIZE r10
231 On entry, lr points to the closure plus 8 bytes, and r10
252 /* Save return address (in r10 due to closure stub wrapper). */
253 SW sp, r10
254 .cfi_return_column r10
255 .cfi_offset r10, 0
258 addli r10, sp, -(CLOSURE_FRAME_SIZE - REG_SIZE)
262 SW r10, sp
271 addi r10, sp, LINKAGE_SIZE
275 STORE_REG(r0, r10)
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ |
| divdi3.S | 23 stmfd sp!, {r10, r11}
24 mov r10, r1, asr #31
26 mov r11, r10
28 eor r0, r0, r10
29 eor r1, r1, r10
35 subs r0, r0, r10
39 eor r2, r10, r4
40 eor r3, r10, r4
46 ldmfd sp!, {r10, r11}
|
| muldi3.S | 20 stmfd sp!, {r8, r10, r11}
28 add r10, ip, lr, lsr #16
29 and ip, r10, r11
35 mov r5, r10, lsr #16
36 add r10, ip, r4, lsr #16
37 and ip, r10, r11
41 add ip, r5, r10, lsr #16
45 mov r10, r4
50 ldmfd sp!, {r8, r10, r11}
|
| /external/webrtc/webrtc/modules/audio_coding/codecs/isac/fix/source/ |
| pitch_filter_armv6.S | 47 mov r10, r7, asl #1
48 add r12, r10 @ &outputBuf[*index2]
49 add r8, r10 @ &inputBuf[*index2]
68 @ r4, r5, r7, r10, r11: scratch
73 ldr r10, [r3], #4 @ ubufQQpos2[*index2 + 0, *index2 + 1]
77 smuad r2, r10, r4
80 ldr r10, [r3], #4
84 smlad r2, r10, r4, r2
85 ldrh r10, [r3], #-14 @ r3 back to &ubufQQpos2[*index2].
88 smlabb r2, r10, r4, r
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/cfi/ |
| cfi-s390x-1.s | 16 .cfi_offset %r10,-80
23 lgr %r10,%r4
29 lgfr %r10,%r10
31 lgr %r4,%r10
|
| /external/libxaac/decoder/armv7/ |
| ixheaacd_fft_15_ld.s | 32 LDRD r10, [r0] @ r10 = buf1a[8] and r11 = buf1a[9]
35 ADD r1, r4, r10 @ r1 = buf1a[2] + buf1a[8]
36 SUB r4, r4, r10 @ r4 = buf1a[2] - buf1a[8]@
37 LDR r10, = C54_55VAL
42 SMULWT r6, r6, r10 @ t = mult32x16in32_shl((r1 - r3), C54)
45 SMULWB r1, r1, r10 @ mult32_shl(r1, C55)
47 LDR r10, = C51_52VAL @
54 SMULWT r2, r2, r10 @ t = mult32_shl((r4 + r2), C51)@
59 SMULWB r4, r4, r10 @ mult32_shl(r4, C52
[all...] |
| ixheaacd_sbr_qmfanal32_winadds_eld.s | 15 MOV r10, #3
41 SUBS r10, r10, #1
64 MOV R10, R2 @
76 SUB R10, R10, #8
105 MOV R2, R10 @
107 MOV R10, R3
116 SUB R10, R10, #
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/s390/ |
| esa-g5.d | 9 .*: 5a 65 af ff [ ]*a %r6,4095\(%r5,%r10\)
10 .*: 6a 65 af ff [ ]*ad %f6,4095\(%r5,%r10\)
11 .*: ed 65 af ff 00 1a [ ]*adb %f6,4095\(%r5,%r10\)
14 .*: 7a 65 af ff [ ]*ae %f6,4095\(%r5,%r10\)
15 .*: ed 65 af ff 00 0a [ ]*aeb %f6,4095\(%r5,%r10\)
18 .*: 4a 65 af ff [ ]*ah %r6,4095\(%r5,%r10\)
20 .*: 5e 65 af ff [ ]*al %r6,4095\(%r5,%r10\)
22 .*: fa 58 5f ff af ff [ ]*ap 4095\(6,%r5\),4095\(9,%r10\)
24 .*: 7e 65 af ff [ ]*au %f6,4095\(%r5,%r10\)
26 .*: 6e 65 af ff [ ]*aw %f6,4095\(%r5,%r10\)
[all...] |
| /external/llvm/test/CodeGen/BPF/ |
| undef.ll | 19 ; CHECK: stb -8(r10), r1
23 ; CHECK: stb -7(r10), r1
27 ; CHECK: stb -6(r10), r1
31 ; CHECK: stb -5(r10), r1
35 ; CHECK: stb -4(r10), r1
39 ; CHECK: stb -3(r10), r1
42 ; CHECK: mov r1, r10
48 ; CHECK: sth 24(r10), r2
49 ; CHECK: sth 22(r10), r2
50 ; CHECK: sth 20(r10), r
[all...] |
| /external/boringssl/src/ssl/test/runner/curve25519/ |
| mul_amd64.s | 37 MOVQ AX,R10
53 ADDQ AX,R10
92 ADDQ AX,R10
104 ADDQ AX,R10
116 ADDQ AX,R10
129 SHLQ $13,R11:R10
130 ANDQ SI,R10
131 ADDQ R9,R10
145 ADDQ R10,DX
158 MOVQ DX,R10
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| swiftself.ll | 7 ; Parameter with swiftself should be allocated to r10.
9 ; CHECK: mov r0, r10
14 ; Check that r10 is used to pass a swiftself argument.
16 ; CHECK: mov r10, r0
23 ; r10 should be saved by the callee even if used for swiftself
25 ; CHECK: push {r10}
27 ; CHECK: pop {r10}
29 call void asm sideeffect "", "~{r10}"()
36 ; OPT-NOT: mov{{.*}}r10
38 ; OPT-NOT: mov{{.*}}r10
[all...] |
| /external/tremolo/Tremolo/ |
| mdctARM.s | 189 LDMFD r12,{r8,r9,r10} @ r8 = step
191 @ r10= wR
200 LDR r6, [r10,#-4]! @ r6 = *--wR
228 LDMFD r12,{r8,r9,r10} @ r8 = step
230 @ r10= wR
239 LDR r6, [r10,#-4]! @ r6 = *--wR
323 LDR r10,[r5],r2,LSL #2 @ r10= T[0] T += step
329 SMLAL r8, r9, r6, r10 @ (r8, r9) += s0*T[0]
332 SMULL r8, r12,r7, r10 @ (r8, r12) = s2*T[0
[all...] |
