| /external/llvm/test/CodeGen/X86/ |
| vector-rotate-128.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
36 ; SSE41-LABEL: var_rotate_v2i64:
37 ; SSE41: # BB#0:
38 ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [64,64]
39 ; SSE41-NEXT: psubq %xmm1, %xmm2
40 ; SSE41-NEXT: movdqa %xmm0, %xmm3
41 ; SSE41-NEXT: psllq %xmm1, %xmm3
42 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
43 ; SSE41-NEXT: movdqa %xmm0, %xmm4
44 ; SSE41-NEXT: psllq %xmm1, %xmm
[all...] |
| vector-idiv.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
47 ; SSE41-LABEL: PR20355:
48 ; SSE41: # BB#0: # %entry
49 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1431655766,1431655766,1431655766,1431655766]
50 ; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
51 ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
52 ; SSE41-NEXT: pmuldq %xmm2, %xmm3
53 ; SSE41-NEXT: pmuldq %xmm1, %xmm0
54 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
55 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7
[all...] |
| vec_minmax_sint.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
34 ; SSE41-LABEL: max_gt_v2i64:
35 ; SSE41: # BB#0:
36 ; SSE41-NEXT: movdqa %xmm0, %xmm2
37 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
38 ; SSE41-NEXT: movdqa %xmm1, %xmm3
39 ; SSE41-NEXT: pxor %xmm0, %xmm3
40 ; SSE41-NEXT: pxor %xmm2, %xmm0
41 ; SSE41-NEXT: movdqa %xmm0, %xmm4
42 ; SSE41-NEXT: pcmpgtd %xmm3, %xmm
[all...] |
| vec_minmax_uint.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
34 ; SSE41-LABEL: max_gt_v2i64:
35 ; SSE41: # BB#0:
36 ; SSE41-NEXT: movdqa %xmm0, %xmm2
37 ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648]
38 ; SSE41-NEXT: movdqa %xmm1, %xmm3
39 ; SSE41-NEXT: pxor %xmm0, %xmm3
40 ; SSE41-NEXT: pxor %xmm2, %xmm0
41 ; SSE41-NEXT: movdqa %xmm0, %xmm4
42 ; SSE41-NEXT: pcmpgtd %xmm3, %xmm
[all...] |
| vec_cmp_sint-128.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
24 ; SSE41-LABEL: eq_v2i64:
25 ; SSE41: # BB#0:
26 ; SSE41-NEXT: pcmpeqq %xmm1, %xmm0
27 ; SSE41-NEXT: retq
122 ; SSE41-LABEL: ne_v2i64:
123 ; SSE41: # BB#0:
124 ; SSE41-NEXT: pcmpeqq %xmm1, %xmm0
125 ; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
126 ; SSE41-NEXT: pxor %xmm1, %xmm
[all...] |
| commute-blend-sse41.ll | 10 %2 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %1, <8 x i16> %a, i8 17)
13 declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind readnone
21 %2 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %1, <4 x float> %a, i8 5)
24 declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i8) nounwind readnone
32 %2 = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %1, <2 x double> %a, i8 1)
35 declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i8) nounwind readnone
|
| sse41-intrinsics-x86-upgrade.ll | 12 %res = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a1, i32 6) ; <<2 x double>> [#uses=1]
15 declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i32) nounwind readnone
23 %res = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a1, i32 7) ; <<4 x float>> [#uses=1]
26 declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i32) nounwind readnone
34 %res = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> %a0, <2 x double> %a1, i32 7) ; <<2 x double>> [#uses=1]
37 declare <2 x double> @llvm.x86.sse41.dppd(<2 x double>, <2 x double>, i32) nounwind readnone
45 %res = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> %a0, <4 x float> %a1, i32 7) ; <<4 x float>> [#uses=1]
48 declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i32) nounwind readnone
56 %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i32 17) ; <<4 x float>> [#uses=1]
59 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnon
[all...] |
| vector-shift-shl-128.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
28 ; SSE41-LABEL: var_shift_v2i64:
29 ; SSE41: # BB#0:
30 ; SSE41-NEXT: movdqa %xmm0, %xmm2
31 ; SSE41-NEXT: psllq %xmm1, %xmm2
32 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
33 ; SSE41-NEXT: psllq %xmm1, %xmm0
34 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
35 ; SSE41-NEXT: retq
95 ; SSE41-LABEL: var_shift_v4i32
[all...] |
| vector-popcnt-128.ll | 5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
68 ; SSE41-LABEL: testv2i64:
69 ; SSE41: # BB#0:
70 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
71 ; SSE41-NEXT: movdqa %xmm0, %xmm2
72 ; SSE41-NEXT: pand %xmm1, %xmm2
73 ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
74 ; SSE41-NEXT: movdqa %xmm3, %xmm4
75 ; SSE41-NEXT: pshufb %xmm2, %xmm4
76 ; SSE41-NEXT: psrlw $4, %xmm
[all...] |
| vec_uint_to_fp.ll | 2 ; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+sse4.1 | FileCheck --check-prefix=CHECK --check-prefix=SSE41 --check-prefix=CST %s
56 ; SSE41: movdqa [[LOWCSTADDR]](%rip), [[LOWVEC:%xmm[0-9]+]]
57 ; SSE41-NEXT: pblendw $85, %xmm0, [[LOWVEC]]
58 ; SSE41-NEXT: psrld $16, %xmm0
59 ; SSE41-NEXT: pblendw $170, [[HIGHCSTADDR]](%rip), %xmm0
60 ; SSE41-NEXT: addps [[MAGICCSTADDR]](%rip), %xmm0
61 ; SSE41-NEXT: addps [[LOWVEC]], %xmm0
62 ; SSE41-NEXT: retq
122 ; SSE41: movdqa {{.*#+}} [[LOWCST:xmm[0-9]+]] = [1258291200,1258291200,1258291200,1258291200]
123 ; SSE41-NEXT: movdqa %xmm0, [[VECLOW:%xmm[0-9]+]
[all...] |
| vec_cmp_uint-128.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
24 ; SSE41-LABEL: eq_v2i64:
25 ; SSE41: # BB#0:
26 ; SSE41-NEXT: pcmpeqq %xmm1, %xmm0
27 ; SSE41-NEXT: retq
122 ; SSE41-LABEL: ne_v2i64:
123 ; SSE41: # BB#0:
124 ; SSE41-NEXT: pcmpeqq %xmm1, %xmm0
125 ; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
126 ; SSE41-NEXT: pxor %xmm1, %xmm
[all...] |
| pmul.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
26 ; SSE41-LABEL: mul_v16i8c:
27 ; SSE41: # BB#0: # %entry
28 ; SSE41-NEXT: pmovsxbw %xmm0, %xmm1
29 ; SSE41-NEXT: pmovsxbw {{.*}}(%rip), %xmm2
30 ; SSE41-NEXT: pmullw %xmm2, %xmm1
31 ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
32 ; SSE41-NEXT: pand %xmm3, %xmm1
33 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
34 ; SSE41-NEXT: pmovsxbw %xmm0, %xmm
[all...] |
| pr20088.ll | 3 declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>)
7 %res = call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> zeroinitializer, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8> %x)
|
| combine-64bit-vec-binop.ll | 1 ; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK -check-prefix=SSE41
13 ; SSE41: paddd
26 ; SSE41: paddw
38 ; SSE41: paddb
51 ; SSE41: psubd
64 ; SSE41: psubw
77 ; SSE41: psubb
90 ; SSE41: pmulld
103 ; SSE41: pmullw
129 ; SSE41: andp
[all...] |
| vec_setcc.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
48 ; SSE41-LABEL: v8i16_icmp_uge:
49 ; SSE41: # BB#0:
50 ; SSE41-NEXT: pmaxuw %xmm0, %xmm1
51 ; SSE41-NEXT: pcmpeqw %xmm1, %xmm0
52 ; SSE41-NEXT: retq
72 ; SSE41-LABEL: v8i16_icmp_ule:
73 ; SSE41: # BB#0:
74 ; SSE41-NEXT: pminuw %xmm0, %xmm1
75 ; SSE41-NEXT: pcmpeqw %xmm1, %xmm
[all...] |
| pmovext.ll | 13 %4 = tail call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %3) nounwind
20 declare <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8>) nounwind readnone
31 %tmp2 = tail call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp1) nounwind
41 %tmp2 = tail call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %tmp1)
45 declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone
|
| vector-shift-ashr-128.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
36 ; SSE41-LABEL: var_shift_v2i64:
37 ; SSE41: # BB#0:
38 ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
39 ; SSE41-NEXT: movdqa %xmm2, %xmm3
40 ; SSE41-NEXT: psrlq %xmm1, %xmm3
41 ; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,0,1]
42 ; SSE41-NEXT: psrlq %xmm4, %xmm2
43 ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
44 ; SSE41-NEXT: movdqa %xmm0, %xmm
[all...] |
| vector-shift-lshr-128.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
28 ; SSE41-LABEL: var_shift_v2i64:
29 ; SSE41: # BB#0:
30 ; SSE41-NEXT: movdqa %xmm0, %xmm2
31 ; SSE41-NEXT: psrlq %xmm1, %xmm2
32 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
33 ; SSE41-NEXT: psrlq %xmm1, %xmm0
34 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
35 ; SSE41-NEXT: retq
106 ; SSE41-LABEL: var_shift_v4i32
[all...] |
| vector-shuffle-variable-128.ll | 4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
93 ; SSE41-LABEL: var_shuffle_v4f32_v4f32_xxxx_i32:
94 ; SSE41: # BB#0:
95 ; SSE41-NEXT: movslq %edi, %rax
96 ; SSE41-NEXT: movslq %esi, %rsi
97 ; SSE41-NEXT: movslq %edx, %rdx
98 ; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
99 ; SSE41-NEXT: movslq %ecx, %rcx
100 ; SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
101 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3
[all...] |
| vector-shuffle-128-v4.ll | 5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
264 ; SSE41-LABEL: shuffle_v4f32_0022:
265 ; SSE41: # BB#0:
266 ; SSE41-NEXT: movsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
267 ; SSE41-NEXT: retq
292 ; SSE41-LABEL: shuffle_v4f32_1133:
293 ; SSE41: # BB#0:
294 ; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
295 ; SSE41-NEXT: retq
353 ; SSE41-LABEL: shuffle_v4i32_0124
[all...] |
| vector-zext.ll | 4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
22 ; SSE41-LABEL: zext_16i8_to_8i16:
23 ; SSE41: # BB#0: # %entry
24 ; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
25 ; SSE41-NEXT: retq
55 ; SSE41-LABEL: zext_16i8_to_16i16:
56 ; SSE41: # BB#0: # %entry
57 ; SSE41-NEXT: movdqa %xmm0, %xmm1
58 ; SSE41-NEXT: pxor %xmm2, %xmm2
59 ; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero (…)
[all...] |
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| vector-ops.ll | 8 ; RUN: | FileCheck --check-prefix=SSE41 %s
10 ; RUN: | FileCheck --check-prefix=SSE41 %s
28 ; SSE41-LABEL: insertelement_v4f32_0
29 ; SSE41: insertps {{.*}},{{.*}},0x0
58 ; SSE41-LABEL: insertelement_v4i32_0
59 ; SSE41: pinsrd {{.*}},{{.*}},0x0
81 ; SSE41-LABEL: insertelement_v4f32_1
82 ; SSE41: insertps {{.*}},{{.*}},0x10
104 ; SSE41-LABEL: insertelement_v4i32_1
105 ; SSE41: pinsrd {{.*}},{{.*}},0x
[all...] |
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| 2008-04-24-pblendw-fold-crash.ll | 1 ; RUN: llc < %s -mattr=+sse41
11 %tmp129 = call <8 x i16> @llvm.x86.sse41.pblendw( <8 x i16> zeroinitializer, <8 x i16> %tmp126, i32 2 ) nounwind ; <<8 x i16>> [#uses=0]
15 declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i32) nounwind
|
| movgs.ll | 1 ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mattr=sse41 | FileCheck %s --check-prefix=X32
2 ; RUN: llc < %s -mtriple=x86_64-linux -mattr=sse41 | FileCheck %s --check-prefix=X64
3 ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=sse41 | FileCheck %s --check-prefix=X64
44 %2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone
58 declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
|
| /external/clang/test/CodeGen/ |
| sse41-builtins.c | 9 // NOTE: This should match the tests in llvm/test/CodeGen/X86/sse41-intrinsics-fast-isel.ll
31 // CHECK: call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}})
37 // CHECK: call <2 x double> @llvm.x86.sse41.blendvpd(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
43 // CHECK: call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
49 // CHECK: call <2 x double> @llvm.x86.sse41.round.pd(<2 x double> %{{.*}}, i32 2)
55 // CHECK: call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %{{.*}}, i32 2)
61 // CHECK: call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 2)
67 // CHECK: call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 2)
164 // CHECK: call <2 x double> @llvm.x86.sse41.dppd(<2 x double> {{.*}}, <2 x double> {{.*}}, i8 7)
170 // CHECK: call <4 x float> @llvm.x86.sse41.dpps(<4 x float> {{.*}}, <4 x float> {{.*}}, i8 7
[all...] |
