| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 246 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32,
250 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
|
| /external/swiftshader/third_party/LLVM/docs/CommandGuide/ |
| FileCheck.pod | 72 define void @sub1(i32* %p, i32 %v) {
74 ; <b>CHECK: sub1:</b>
100 is checking for the "sub1:" and "inc4:" labels, it will not match unless there
|
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| highbd_loopfilter_neon.c | 121 static INLINE void filter_update(const uint16x8_t sub0, const uint16x8_t sub1,
125 *sum = vsubq_u16(*sum, sub1);
131 const uint16x8_t sub1,
135 filter_update(sub0, sub1, add0, add1, sum);
140 const uint16x8_t flat, const uint16x8_t sub0, const uint16x8_t sub1,
143 filter_update(sub0, sub1, add0, add1, sum);
|
| /art/libartbase/base/ |
| transform_array_ref_test.cc | 82 auto sub1 = [](ValueHolder& h) { return h.value - 1; }; local
86 auto taref = MakeTransformArrayRef(input, sub1);
|
| /external/vulkan-validation-layers/libs/glm/detail/ |
| intrinsic_common.inl | 276 __m128 sub1 = _mm_sub_ps(edge1, edge0);
277 __m128 div0 = _mm_sub_ps(sub0, sub1);
|
| /prebuilts/ndk/r16/sources/third_party/vulkan/src/libs/glm/detail/ |
| intrinsic_common.inl | 276 __m128 sub1 = _mm_sub_ps(edge1, edge0);
277 __m128 div0 = _mm_sub_ps(sub0, sub1);
|
| /art/compiler/optimizing/ |
| load_store_analysis_test.cc | 200 HInstruction* sub1 = new (GetAllocator()) HSub(DataType::Type::kInt32, index, c1); local
212 new (GetAllocator()) HArraySet(array, sub1, c0, DataType::Type::kInt32, 0);
223 entry->AddInstruction(sub1);
260 loc2 = heap_location_collector.GetArrayHeapLocation(array, sub1);
|
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-powerpc/ |
| vle-reloc-2.d | 5 01800094 <sub1>:
|
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-tic6x/ |
| shlib-1.rd | 111 .* 10000080 0 FUNC LOCAL HIDDEN 9 sub1
|
| shlib-1b.rd | 111 .* 10000080 0 FUNC LOCAL HIDDEN 9 sub1
|
| shlib-1r.rd | 111 .* 10000080 0 FUNC LOCAL HIDDEN 9 sub1
|
| shlib-1rb.rd | 111 .* 10000080 0 FUNC LOCAL HIDDEN 9 sub1
|
| static-app-1.rd | 98 .* 10000000 0 FUNC LOCAL HIDDEN 7 sub1
|
| static-app-1b.rd | 98 .* 10000000 0 FUNC LOCAL HIDDEN 7 sub1
|
| static-app-1r.rd | 96 .* 10000000 0 FUNC LOCAL HIDDEN 7 sub1
|
| static-app-1rb.rd | 96 .* 10000000 0 FUNC LOCAL HIDDEN 7 sub1
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstructions.td | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 377 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
379 /// - vreg1:sub1, sub0
380 /// - vreg2<:0>, sub1
397 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
398 /// - vreg1:sub1, sub0
416 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
418 /// - InsertedReg: vreg1:sub1, sub3
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 380 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
382 /// - vreg1:sub1, sub0
383 /// - vreg2<:0>, sub1
400 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
401 /// - vreg1:sub1, sub0
419 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
421 /// - InsertedReg: vreg1:sub1, sub3
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/Target/ |
| TargetInstrInfo.h | 416 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
418 /// - vreg1:sub1, sub0
419 /// - vreg2<:0>, sub1
436 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
437 /// - vreg1:sub1, sub0
455 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
457 /// - InsertedReg: vreg1:sub1, sub3
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/Target/ |
| TargetInstrInfo.h | 416 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
418 /// - vreg1:sub1, sub0
419 /// - vreg2<:0>, sub1
436 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
437 /// - vreg1:sub1, sub0
455 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
457 /// - InsertedReg: vreg1:sub1, sub3
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/Target/ |
| TargetInstrInfo.h | 425 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
427 /// - vreg1:sub1, sub0
428 /// - vreg2<:0>, sub1
445 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
446 /// - vreg1:sub1, sub0
463 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
465 /// - InsertedReg: vreg1:sub1, sub3
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/Target/ |
| TargetInstrInfo.h | 425 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
427 /// - vreg1:sub1, sub0
428 /// - vreg2<:0>, sub1
445 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
446 /// - vreg1:sub1, sub0
463 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
465 /// - InsertedReg: vreg1:sub1, sub3
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/Target/ |
| TargetInstrInfo.h | 425 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
427 /// - vreg1:sub1, sub0
428 /// - vreg2<:0>, sub1
445 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
446 /// - vreg1:sub1, sub0
463 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
465 /// - InsertedReg: vreg1:sub1, sub3
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/Target/ |
| TargetInstrInfo.h | 425 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
427 /// - vreg1:sub1, sub0
428 /// - vreg2<:0>, sub1
445 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
446 /// - vreg1:sub1, sub0
463 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
465 /// - InsertedReg: vreg1:sub1, sub3
[all...] |
