| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/d30v/ |
| inst.d | 237 718: 08501083 885b2cda subb.s r1, r2, r3 -> subb.s r50, r51, 0x1a
238 720: 885b2cf7 8ab1beef subb.l r50, r51, 0xdeadbeef
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4.h | 228 EMIT2(SUBB)
|
| brw_eu.h | 188 ALU2(SUBB)
|
| brw_fs_builder.h | 492 ALU2_ACC(SUBB)
|
| brw_vec4_builder.h | 438 ALU2_ACC(SUBB)
|
| /external/swiftshader/third_party/LLVM/test/MC/X86/ |
| x86-64.s | 30 // CHECK: subb %al, %al
31 subb %al, %al
74 // CHECK: subb %al, %bl
75 subb %al, %bl
|
| /external/syslinux/core/lzo/ |
| lzo1x_d.ash | 49 subb $17-NN,%al
|
| /external/syslinux/gpxe/src/arch/i386/prefix/ |
| dskprefix.S | 279 subb %cl,%al
|
| /external/zlib/src/contrib/inflate86/ |
| inffast.S | 468 subb %ah, bits_r /* bits -= this.bits */
524 subb %cl, bits_r
568 subb %ah, bits_r /* bits -= this.bits */
604 subb %cl, bits_r
[all...] |
| /toolchain/binutils/binutils-2.27/include/opcode/ |
| m88k.h | 259 #define SUBB ADD+2
|
| /toolchain/binutils/binutils-2.27/zlib/contrib/inflate86/ |
| inffast.S | 468 subb %ah, bits_r /* bits -= this.bits */
524 subb %cl, bits_r
568 subb %ah, bits_r /* bits -= this.bits */
604 subb %cl, bits_r
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| z8k-opc.h | [all...] |
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/Target/ |
| TargetRegisterInfo.h | 415 /// MaskB = getSubRegIndexLaneMask(SubB);
418 /// SubB.
638 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
648 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
657 const TargetRegisterClass *RCB, unsigned SubB,
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/Target/ |
| TargetRegisterInfo.h | 415 /// MaskB = getSubRegIndexLaneMask(SubB);
418 /// SubB.
638 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
648 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
657 const TargetRegisterClass *RCB, unsigned SubB,
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/Target/ |
| TargetRegisterInfo.h | 415 /// MaskB = getSubRegIndexLaneMask(SubB);
418 /// SubB.
638 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
648 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
657 const TargetRegisterClass *RCB, unsigned SubB,
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/Target/ |
| TargetRegisterInfo.h | 415 /// MaskB = getSubRegIndexLaneMask(SubB);
418 /// SubB.
638 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
648 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
657 const TargetRegisterClass *RCB, unsigned SubB,
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4579689/include/llvm/Target/ |
| TargetRegisterInfo.h | 415 /// MaskB = getSubRegIndexLaneMask(SubB);
418 /// SubB.
638 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
648 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
657 const TargetRegisterClass *RCB, unsigned SubB,
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4630689/include/llvm/Target/ |
| TargetRegisterInfo.h | 415 /// MaskB = getSubRegIndexLaneMask(SubB);
418 /// SubB.
638 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
648 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
657 const TargetRegisterClass *RCB, unsigned SubB,
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4639204/include/llvm/Target/ |
| TargetRegisterInfo.h | 415 /// MaskB = getSubRegIndexLaneMask(SubB);
418 /// SubB.
638 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
648 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
657 const TargetRegisterClass *RCB, unsigned SubB,
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4691093/include/llvm/Target/ |
| TargetRegisterInfo.h | 415 /// MaskB = getSubRegIndexLaneMask(SubB);
418 /// SubB.
638 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
648 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
657 const TargetRegisterClass *RCB, unsigned SubB,
[all...] |
| /external/llvm/test/MC/X86/ |
| x86-64.s | 30 // CHECK: subb %al, %al
31 subb %al, %al
77 // CHECK: subb %al, %bl
78 subb %al, %bl
[all...] |
| /external/zlib/src/contrib/amd64/ |
| amd64-match.S | 384 LenLower: subb $1, %al
|
| /external/zlib/src/contrib/asm686/ |
| match.S | 282 LenLower: subb $1, %al
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/tic54x/ |
| opcodes.d | 279 10e: 0e90 subb \*ar0\+,a
|
| /toolchain/binutils/binutils-2.27/zlib/contrib/amd64/ |
| amd64-match.S | 384 LenLower: subb $1, %al
|
