| /external/libavc/common/armv8/ |
| ih264_inter_pred_luma_horz_qpel_av8.s | 117 sxtw x2, w2
118 sxtw x3, w3
119 sxtw x4, w4
120 sxtw x5, w5
[all...] |
| ih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s | 128 sxtw x2, w2
129 sxtw x3, w3
130 sxtw x4, w4
131 sxtw x5, w5
|
| ih264_inter_pred_luma_horz_qpel_vert_qpel_av8.s | 125 sxtw x2, w2
126 sxtw x3, w3
127 sxtw x4, w4
128 sxtw x5, w5
[all...] |
| /external/llvm/test/MC/Hexagon/instructions/ |
| xtype_alu.s | 204 r17:16 = sxtw(r21)
|
| /prebuilts/go/darwin-x86/src/cmd/asm/internal/asm/testdata/ |
| arm64.s | 34 ADDW R2.SXTW, R10, R12 // 4cc1220b
|
| /prebuilts/go/linux-x86/src/cmd/asm/internal/asm/testdata/ |
| arm64.s | 34 ADDW R2.SXTW, R10, R12 // 4cc1220b
|
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Assembler.cpp | 1007 LOG_INSTR("%s W%d, [X%d, W%d, SXTW #0]\n",
1013 LOG_INSTR("%s X%d, [X%d, W%d, SXTW #0]\n",
1049 LOG_INSTR("ADD X%d, X%d, W%d, SXTW #%d\n", Rd, Rn, Rm, amount);
1060 LOG_INSTR("SUB X%d, X%d, W%d, SXTW #%d\n", Rd, Rn, Rm, amount);
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| aarch64-asm-2.c | 114 case 614: /* sxtw */
|
| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 466 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
519 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
[all...] |
| macro-assembler-arm64-inl.h | 1158 void MacroAssembler::Sxtw(const Register& rd, const Register& rn) {
1161 sxtw(rd, rn);
[all...] |
| /external/llvm/test/MC/AArch64/ |
| basic-a64-diagnostics.s | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| basic-a64-instructions.txt | 637 # CHECK: sxtw x3, w30
[all...] |
| /external/llvm/test/CodeGen/Hexagon/intrinsics/ |
| xtype_alu.ll | 552 declare i64 @llvm.hexagon.A2.sxtw(i32)
554 %z = call i64 @llvm.hexagon.A2.sxtw(i32 %a)
557 ; CHECK: = sxtw({{.*}})
|
| /external/v8/src/compiler/arm64/ |
| code-generator-arm64.cc | 123 return Operand(InputRegister32(index), SXTW);
153 return Operand(InputRegister64(index), SXTW);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 676 Addr.setExtendType(AArch64_AM::SXTW);
760 Addr.setExtendType(AArch64_AM::SXTW);
818 Addr.setExtendType(AArch64_AM::SXTW);
[all...] |
| /external/libavc/encoder/armv8/ |
| ih264e_half_pel_av8.s | 89 sxtw x2, w2
90 sxtw x3, w3
268 sxtw x3, w3
269 sxtw x4, w4
[all...] |
| /external/libhevc/common/arm64/ |
| ihevc_intra_pred_chroma_mode_27_to_33.s | 111 sxtw x9,w9
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 366 SXTW,
|
| /external/llvm/test/MC/Disassembler/Hexagon/ |
| xtype_alu.txt | 204 # CHECK: r17:16 = sxtw(r21)
|
| /external/vixl/src/aarch64/ |
| operands-aarch64.h | 752 // where <extend> is one of {UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX}.
|
| /prebuilts/vndk/v27/arm/arch-arm-armv7-a-neon/shared/vndk-core/ |
| libvixl-arm64.so | |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| diagnostic.l | 75 [^:]*:77: Error: register offset not allowed in pre-indexed addressing mode at operand 2 -- `prfm pldl3strm,\[sp,w0,sxtw#3\]!'
|
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| tables.go | 391 SXTW
860 SXTW: "SXTW",
1048 // SXTW <Xd>, <Wn>
1049 {0xfffffc00, 0x93407c00, SXTW, instArgs{arg_Xd, arg_Wn}, nil},
[all...] |
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| tables.go | 391 SXTW
860 SXTW: "SXTW",
1048 // SXTW <Xd>, <Wn>
1049 {0xfffffc00, 0x93407c00, SXTW, instArgs{arg_Xd, arg_Wn}, nil},
[all...] |
| /external/capstone/arch/AArch64/ |
| AArch64InstPrinter.c | 109 AsmMnemonic = "sxtw";
[all...] |
