| /external/llvm/test/Transforms/IndVarSimplify/ |
| loop_evaluate_4.ll | 9 %v.01.0 = phi i32 [ 0, %entry ], [ %tmp4, %bb7 ] ; <i32> [#uses=1]
12 %tmp4 = add i32 %tmp2, %v.01.0 ; <i32> [#uses=2]
18 ret i32 %tmp4
|
| /external/swiftshader/third_party/LLVM/test/Transforms/IndVarSimplify/ |
| 2006-03-31-NegativeStride.ll | 12 %a.0.0 = phi i32 [ 10, %entry ], [ %tmp4, %cond_true ] ; <i32> [#uses=2]
15 %tmp4 = add i32 %a.0.0, -1 ; <i32> [#uses=2]
16 %tmp = icmp sgt i32 %tmp4, 7 ; <i1> [#uses=1]
|
| loop_evaluate_3.ll | 10 %x.03.0 = phi i32 [ 0, %entry ], [ %tmp4, %bb5 ] ; <i32> [#uses=1]
12 %tmp4 = add i32 %x.03.0, 1 ; <i32> [#uses=2]
13 icmp slt i32 %tmp4, 200000 ; <i1>:0 [#uses=1]
|
| loop_evaluate_4.ll | 9 %v.01.0 = phi i32 [ 0, %entry ], [ %tmp4, %bb7 ] ; <i32> [#uses=1]
12 %tmp4 = add i32 %tmp2, %v.01.0 ; <i32> [#uses=2]
18 ret i32 %tmp4
|
| /frameworks/ml/nn/tools/test_generator/tests/P_float/ |
| stdout.txt.expect | 9 auto tmp4 = model->addOperand(&type0);
11 model->addOperation(ANEURALNETWORKS_ADD, {operand1, operand2}, {tmp4});
12 model->addOperation(ANEURALNETWORKS_ADD, {operand3, tmp4}, {operand4});
|
| /external/webrtc/webrtc/modules/audio_coding/codecs/isac/fix/source/ |
| pitch_estimator_mips.c | 34 int32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; local
44 "lh %[tmp4], 6(%[tmp_in]) \n\t"
55 "mul %[tmp8], %[tmp4], %[tmp8] \n\t"
56 "mul %[tmp4], %[tmp4], %[tmp4] \n\t"
65 "srav %[tmp4], %[tmp4], %[scaling] \n\t"
72 "addu %[ysum32], %[ysum32], %[tmp4] \n\t"
79 [tmp4] "=&r" (tmp4), [tmp5] "=&r" (tmp5), [tmp6] "=&r" (tmp6)
105 int32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; local
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| vcge.ll | 9 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
10 ret <8 x i8> %tmp4
19 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
20 ret <4 x i16> %tmp4
29 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
30 ret <2 x i32> %tmp4
39 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
40 ret <8 x i8> %tmp4
49 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
50 ret <4 x i16> %tmp4
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| fneg.ll | 6 %tmp4 = fmul double %tmp2, %d ; <double> [#uses=1]
8 %tmp9 = fsub double %tmp7, %tmp4 ; <double> [#uses=1]
|
| /external/llvm/test/CodeGen/X86/ |
| insertelement-legalize.ll | 6 %tmp4 = insertelement <2 x i64> %val, i64 %x, i32 0 ; <<2 x i64>> [#uses=1]
7 %add = add <2 x i64> %tmp4, %val ; <<2 x i64>> [#uses=1]
|
| nobt.ll | 11 %tmp4 = icmp eq i32 %tmp3, %tmp2 ; <i1> [#uses=1]
12 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
27 %tmp4 = icmp eq i32 %tmp2, %tmp3 ; <i1> [#uses=1]
28 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
43 %tmp4 = icmp ne i32 %tmp2, %tmp3 ; <i1> [#uses=1]
44 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
59 %tmp4 = icmp ne i32 %tmp2, %tmp3 ; <i1> [#uses=1]
60 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
| /external/llvm/test/Transforms/InstCombine/ |
| 2006-10-20-mask.ll | 8 %tmp4 = zext i32 %tmp3 to i64 ; <i64> [#uses=1]
9 ret i64 %tmp4
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| 2008-03-05-SxtInRegBug.ll | 8 %tmp4.i.i = icmp slt i8 %tmp3.i.i, 0 ; <i1> [#uses=1]
9 br i1 %tmp4.i.i, label %bb2, label %bb3
|
| fnmul.ll | 8 %tmp4 = fmul double %tmp2, %b ; <double> [#uses=1]
9 ret double %tmp4
|
| ldr_post.ll | 8 %tmp4 = sub i32 %tmp1, %c ; <i32> [#uses=1]
9 %tmp5 = mul i32 %tmp4, %tmp3 ; <i32> [#uses=1]
|
| machine-cse-cmp.ll | 16 %tmp4 = add i32 %tmp2, %tmp3
17 ret i32 %tmp4
|
| vcge.ll | 9 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
10 ret <8 x i8> %tmp4
19 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
20 ret <4 x i16> %tmp4
29 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
30 ret <2 x i32> %tmp4
39 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
40 ret <8 x i8> %tmp4
49 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
50 ret <4 x i16> %tmp4
[all...] |
| /external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/ |
| fneg.ll | 6 %tmp4 = fmul double %tmp2, %d ; <double> [#uses=1]
8 %tmp9 = fsub double %tmp7, %tmp4 ; <double> [#uses=1]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| thumb2-ldr_post.ll | 8 %tmp4 = sub i32 %tmp1, 8 ; <i32> [#uses=1]
9 %tmp5 = mul i32 %tmp4, %tmp3 ; <i32> [#uses=1]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| insertelement-legalize.ll | 6 %tmp4 = insertelement <2 x i64> %val, i64 %x, i32 0 ; <<2 x i64>> [#uses=1]
7 %add = add <2 x i64> %tmp4, %val ; <<2 x i64>> [#uses=1]
|
| lea-2.ll | 9 %tmp4 = add i32 %tmp3, %tmp1 ; <i32> [#uses=1]
10 ret i32 %tmp4
|
| mmx-insert-element.ll | 7 %tmp4 = bitcast <2 x i32> %tmp3 to x86_mmx
8 ret x86_mmx %tmp4
|
| nobt.ll | 11 %tmp4 = icmp eq i32 %tmp3, %tmp2 ; <i1> [#uses=1]
12 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
27 %tmp4 = icmp eq i32 %tmp2, %tmp3 ; <i1> [#uses=1]
28 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
43 %tmp4 = icmp ne i32 %tmp2, %tmp3 ; <i1> [#uses=1]
44 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
59 %tmp4 = icmp ne i32 %tmp2, %tmp3 ; <i1> [#uses=1]
60 br i1 %tmp4, label %bb, label %UnifiedReturnBlock
|
| vec_insert-9.ll | 7 %tmp4 = insertelement <4 x i32> %tmp3, i32 %idx, i32 3 ; <<4 x i32>> [#uses=1]
8 ret <4 x i32> %tmp4
|
| /external/swiftshader/third_party/LLVM/test/Transforms/DeadArgElim/ |
| dead_vaargs.ll | 5 %tmp4 = tail call i32 (i32, ...)* @foo( i32 %A, i32 %A, i32 %A, i32 %A, i64 47, double 1.000000e+00 ) ; <i32> [#uses=1]
6 ret i32 %tmp4
|
| /external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
| 2006-10-20-mask.ll | 8 %tmp4 = zext i32 %tmp3 to i64 ; <i64> [#uses=1]
9 ret i64 %tmp4
|
