| /external/llvm/test/Analysis/Delinearization/ |
| undef.ll | 7 br i1 undef, label %for.cond55.preheader, label %for.end324
11 br i1 undef, label %for.cond58.preheader, label %for.inc322
15 br i1 undef, label %for.body60, label %for.end
19 %0 = mul i64 %iz.069, undef
21 %tmp6 = mul i64 %tmp5, undef
22 %arrayidx69.sum = add i64 undef, %tmp6
30 br i1 undef, label %for.cond58.preheader, label %for.inc322
34 br i1 undef, label %for.cond55.preheader, label %for.end324
|
| /external/llvm/test/Analysis/PostDominators/ |
| pr6047_b.ll | 4 br i1 undef, label %a, label %bb3.i
7 br i1 undef, label %bb35, label %bb3.i
|
| /external/llvm/test/CodeGen/AArch64/ |
| aarch64_tree_tests.ll | 20 %and = and <8 x i16> <i16 0, i16 undef, i16 undef, i16 0, i16 0, i16 undef, i16 undef, i16 0>, %a
38 %or = or <8 x i16> <i16 -1, i16 undef, i16 undef, i16 -1, i16 -1, i16 undef, i16 undef, i16 -1>, %a
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| hsa-group-segment.ll | 3 @internal_group = internal addrspace(3) global i32 undef
4 @external_group = addrspace(3) global i32 undef
|
| /external/llvm/test/CodeGen/ARM/ |
| 2009-05-05-DAGCombineBug.ll | 9 %tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null) ; <i1> [#uses=0]
|
| 2010-04-14-SplitVector.ll | 6 br i1 undef, label %bb9, label %bb10
14 %0 = phi i32 [ %tmp64, %bb9 ], [ undef, %bb ]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| in-asm-f64-reg.ll | 7 %0 = tail call double* asm sideeffect "qvstfdux $2,$0,$1", "=b,{r7},{f11},0,~{memory}"(i32 64, double undef, double* undef)
|
| sdag-ppcf128.ll | 7 br i1 undef, label %if, label %else
10 store { ppc_fp128, ppc_fp128 } zeroinitializer, { ppc_fp128, ppc_fp128 }* undef
|
| /external/llvm/test/CodeGen/Thumb2/ |
| 2009-08-04-SubregLoweringBug2.ll | 11 br i1 undef, label %bb14, label %bb3.preheader
17 br i1 undef, label %bb11, label %bb5
20 %0 = fmul float undef, 0x41E0000000000000 ; <float> [#uses=1]
22 store i32 %1, i32* undef, align 4
23 br i1 undef, label %generate_patient.exit, label %generate_patient.exit.thread
29 br i1 undef, label %bb14, label %bb12
32 br i1 undef, label %bb.i, label %bb1.i
41 ret %struct.List* undef
|
| /external/llvm/test/CodeGen/X86/ |
| 2007-05-17-ShuffleISelBug.ll | 10 %tmp633 = shufflevector <8 x i16> zeroinitializer, <8 x i16> undef, <8 x i32> < i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7 >
16 %tmp838 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp832, <8 x i16> < i16 8, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef > )
|
| 2010-01-05-ZExt-Shl.ll | 9 %t1 = icmp ne i8 undef, 0
10 %t2 = icmp eq i8 undef, 14
|
| avx512-i1test.ll | 12 br i1 undef, label %L_10, label %L_10
15 br i1 undef, label %L_30, label %bb56
21 %r111 = load i64, i64* undef, align 8
22 br i1 undef, label %bb51, label %bb35
25 br i1 undef, label %L_19, label %bb37
34 br i1 undef, label %bb51, label %bb42
37 %r136 = select i1 %"$V_S25.0", i32* undef, i32* undef
|
| crash-nosse.ll | 5 ; This test case produces INSERT_SUBREG 0, <undef> instructions that
9 %Shuff6 = shufflevector <32 x i32> undef, <32 x i32> undef, <32 x i32> <i32 27, i32 29, i32 31, i32 undef, i32 undef, i32 37, i32 39, i32 41, i32 undef, i32 45, i32 47, i32 49, i32 51, i32 53, i32 55, i32 57, i32 undef, i32 61, i32 63, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 undef, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25>
|
| promote-trunc.ll | 4 %F = load <4 x i64>, <4 x i64>* undef
6 %H = load <4 x i64>, <4 x i64>* undef
|
| /external/llvm/test/Transforms/DeadArgElim/ |
| variadic_safety.ll | 20 %res = call i32(i32, i32, ...) @va_func(i32 %in, i32 %in, [6 x i32] undef, i32* byval %stacked)
22 ; CHECK: call i32 (i32, i32, ...) @va_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval %stacked)
35 call i32 (i32, i32, ...) @va_deadret_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval %stacked)
37 ; CHECK: call void (i32, i32, ...) @va_deadret_func(i32 undef, i32 undef, [6 x i32] undef, i32* byval %stacked)
|
| /external/mesa3d/src/util/ |
| rgtc.c | 45 #undef TAG
46 #undef TYPE
47 #undef T_MIN
48 #undef T_MAX
57 #undef TAG
58 #undef TYPE
59 #undef T_MIN
60 #undef T_MAX
|
| /external/strace/linux/aarch64/ |
| set_error.c | 4 #undef arch_set_success
5 #undef arch_set_error
|
| /external/swiftshader/third_party/LLVM/test/Analysis/PostDominators/ |
| pr6047_b.ll | 4 br i1 undef, label %a, label %bb3.i
7 br i1 undef, label %bb35, label %bb3.i
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| 2009-05-05-DAGCombineBug.ll | 9 %tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null) ; <i1> [#uses=0]
|
| 2010-04-14-SplitVector.ll | 6 br i1 undef, label %bb9, label %bb10
14 %0 = phi i32 [ %tmp64, %bb9 ], [ undef, %bb ]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/ |
| 2009-08-15-SetCC-Undef.ll | 3 ; An undef argument causes a setugt node to escape instruction selection.
7 %tmp306307 = trunc i32 undef to i8 ; <i8> [#uses=1]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| 2009-08-04-SubregLoweringBug2.ll | 11 br i1 undef, label %bb14, label %bb3.preheader
17 br i1 undef, label %bb11, label %bb5
20 %0 = fmul float undef, 0x41E0000000000000 ; <float> [#uses=1]
22 store i32 %1, i32* undef, align 4
23 br i1 undef, label %generate_patient.exit, label %generate_patient.exit.thread
29 br i1 undef, label %bb14, label %bb12
32 br i1 undef, label %bb.i, label %bb1.i
41 ret %struct.List* undef
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| 2010-01-05-ZExt-Shl.ll | 9 %t1 = icmp ne i8 undef, 0
10 %t2 = icmp eq i8 undef, 14
|
| avx-shuffle.ll | 5 %b = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 undef, i32 undef>
|
| promote-trunc.ll | 4 %F = load <4 x i64>* undef
6 %H = load <4 x i64>* undef
|
