| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.td | 73 def v2i64 : ValueType<128, 46>; // 2 x i64 vector value
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| /external/llvm/test/CodeGen/SystemZ/ |
| vec-abs-04.ll | 1 ; Test v2i64 absolute.
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| vec-move-02.ll | 32 ; Test v2i64 loads.
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| vec-move-03.ll | 32 ; Test v2i64 stores.
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| vec-perm-07.ll | 145 ; We use VPDI for v2i64 shuffles.
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| vec-sub-01.ll | 32 ; Test a v2i64 subtraction.
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCCallingConv.td | 59 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZRegisterInfo.td | 189 def GR128 : RegisterClass<"SystemZ", [v2i64], 128, (add R0Q, R2Q, R4Q,
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| SystemZISelDAGToDAG.cpp | 614 ResVT = MVT::v2i64;
619 ResVT = MVT::v2i64;
701 ResVT = MVT::v2i64;
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| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ValueTypes.td | 73 def v2i64 : ValueType<128, 46>; // 2 x i64 vector value
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| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ValueTypes.td | 73 def v2i64 : ValueType<128, 46>; // 2 x i64 vector value
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| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 178 case MVT::v2i64: return "v2i64";
256 case MVT::v2i64: return VectorType::get(Type::getInt64Ty(Context), 2);
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| /external/llvm/test/CodeGen/ARM/ |
| cttz_vector.ll | 21 declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
202 %tmp = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 false)
380 %tmp = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 true)
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| /external/llvm/test/CodeGen/Mips/msa/ |
| shuffle.ll | 758 ; ilvr.d and ilvev.d are equivalent for v2i64
816 ; ilvr.d and splati.d are equivalent for v2i64
874 ; ilvr.d and splati.d are equivalent for v2i64
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUOperands.td | 389 // immediate constant load for v2i64 vectors.
401 // immediate constant load for v2i64 vectors.
413 // immediate constant load for v2i64 vectors.
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| /external/llvm/test/CodeGen/X86/ |
| bswap-vector.ll | 12 declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
111 %r = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %v)
319 %bs1 = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %v)
320 %bs2 = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %bs1)
424 %r = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> <i64 255, i64 -1>)
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| vector-popcnt-128.ll | 97 %out = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %in)
412 %out = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> <i64 256, i64 -1>)
458 declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
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| /external/clang/test/CodeGen/ |
| aarch64-poly64.c | 284 // CHECK: [[VLD2:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2.v2i64.p0v2i64(<2 x i64>* [[TMP2]])
320 // CHECK: [[VLD3:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3.v2i64.p0v2i64(<2 x i64>* [[TMP2]])
356 // CHECK: [[VLD4:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0v2i64(<2 x i64>* [[TMP2]])
412 // CHECK: call void @llvm.aarch64.neon.st2.v2i64.p0i8(<2 x i64> [[TMP7]], <2 x i64> [[TMP8]], i8* [[TMP2]])
472 // CHECK: call void @llvm.aarch64.neon.st3.v2i64.p0i8(<2 x i64> [[TMP9]], <2 x i64> [[TMP10]], <2 x i64> [[TMP11]], i8* [[TMP2]])
542 // CHECK: call void @llvm.aarch64.neon.st4.v2i64.p0i8(<2 x i64> [[TMP11]], <2 x i64> [[TMP12]], <2 x i64> [[TMP13]], <2 x i64> [[TMP14]], i8* [[TMP2]])
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 570 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
574 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
619 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
620 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
621 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
623 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
626 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
627 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
628 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
630 setOperationAction(ISD::SETCC, MVT::v2i64, Custom)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrAVX512.td | 78 !if (!eq (Size, 128), "v2i64",
84 !if (!eq (Size, 128), "v2i64",
[all...] |
| X86InstrMMX.td | 307 (i64 (extractelt (v2i64 VR128:$src),
314 (v2i64
644 [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZOperators.td | 129 [SDTCisVT<0, v2i64>,
[all...] |
| /external/libvpx/libvpx/vpx_dsp/mips/ |
| fwd_txfm_msa.h | 331 v2i64 tp0_m, tp1_m, tp2_m, tp3_m; \
|
| vpx_convolve8_msa.c | 255 hz_out3 = (v8u16)__msa_pckod_d((v2i64)hz_out4, (v2i64)hz_out2);
294 hz_out7 = (v8u16)__msa_pckod_d((v2i64)hz_out8, (v2i64)hz_out6);
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-neon-simd-shift.ll | 612 declare <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32)
618 declare <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64>, i32)
624 declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double>, i32)
630 declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double>, i32)
|
