| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| vld3.ll | 19 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32)
150 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*, i32) nounwind readonly
|
| vsra.ll | 168 %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
208 %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
323 declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
328 declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
|
| vldlane.ll | 93 %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
191 declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
213 %tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
326 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
349 %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
366 %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
481 declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
|
| /external/llvm/test/CodeGen/AArch64/ |
| fp16-vector-nvcast.ll | 25 ; Test pattern (v4f16 (AArch64NvCast (v8i8 FPR64:$src)))
|
| arm64-indexed-vector-ldst.ll | 639 %ld2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0i8(i8* %A)
648 %ld2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0i8(i8* %A)
654 declare { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0i8(i8*)
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| vsra.ll | 168 %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
208 %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
323 declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
328 declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
|
| vldlane.ll | 105 %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
203 declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
225 %tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
338 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
361 %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
378 %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
493 declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
|
| vadd.ll | 98 %tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
120 declare <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
|
| vbsl.ll | 112 %vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind
198 declare <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
|
| vector-DAGCombine.ll | 81 tail call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* undef, <8 x i8> %4, i32 1)
85 declare void @llvm.arm.neon.vst1.p0i8.v8i8(i8*, <8 x i8>, i32) nounwind
|
| vsub.ll | 125 %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
147 declare <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
|
| /external/llvm/test/CodeGen/SystemZ/ |
| vec-and-03.ll | 27 ; Test a v8i8->v8i16 extension.
|
| vec-move-15.ll | 21 ; Test a v8i8->v8i16 extension.
|
| vec-move-16.ll | 21 ; Test a v8i8->v8i16 extension.
|
| vec-move-17.ll | 21 ; Test a v8i16->v8i8 truncation.
|
| vec-move-02.ll | 131 ; Test v8i8 loads.
|
| vec-move-03.ll | 131 ; Test v8i8 stores.
|
| vec-sub-01.ll | 107 ; Test a v8i8 subtraction, which gets promoted to v16i8.
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ValueTypes.td | 37 def v8i8 : ValueType<64 , 14>; // 8 x i8 vector value
|
| /external/llvm/test/Analysis/CostModel/X86/ |
| cast.ll | 65 %C.v8i8.z = zext <8 x i8> undef to <8 x i32>
68 %C.v8i8.s = sext <8 x i8> undef to <8 x i32>
|
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.td | 48 def v8i8 : ValueType<64 , 24>; // 8 x i8 vector value
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ValueTypes.td | 48 def v8i8 : ValueType<64 , 24>; // 8 x i8 vector value
|
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ValueTypes.td | 48 def v8i8 : ValueType<64 , 24>; // 8 x i8 vector value
|
| /external/llvm/include/llvm/IR/ |
| IntrinsicsARM.td | 204 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
205 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
206 // Overall, the classes range from 2 to 6 v8i8 arguments.
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 156 case MVT::v8i8: return "v8i8";
234 case MVT::v8i8: return VectorType::get(Type::getInt8Ty(Context), 8);
|
