| /external/vixl/test/aarch32/ |
| test-simulator-cond-rd-operand-rn-t32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
712 } // namespace vixl
|
| test-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
495 } // namespace vixl
|
| test-assembler-cond-rd-sp-operand-imm8-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
493 } // namespace vixl
|
| test-macro-assembler-cond-rd-rn-a32.cc | 1 // Copyright 2016, VIXL authors
51 namespace vixl { namespace
[all...] |
| test-macro-assembler-cond-rd-rn-pc-a32.cc | 1 // Copyright 2016, VIXL authors
51 namespace vixl { namespace
[all...] |
| test-macro-assembler-cond-rd-rn-t32.cc | 1 // Copyright 2016, VIXL authors
51 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-rm-ge-a32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
697 } // namespace vixl
|
| test-simulator-cond-rd-rn-rm-ge-t32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
697 } // namespace vixl
|
| test-simulator-cond-rd-rn-rm-q-a32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
681 } // namespace vixl
|
| test-simulator-cond-rd-rn-rm-q-t32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
681 } // namespace vixl
|
| test-simulator-cond-rd-rn-rm-sel-a32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
676 } // namespace vixl
|
| test-simulator-cond-rd-rn-rm-sel-t32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
676 } // namespace vixl
|
| test-simulator-cond-rdlow-operand-imm8-t32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
[all...] |
| test-simulator-rd-rn-rm-a32.cc | 1 // Copyright 2016, VIXL authors
111 namespace vixl { namespace
663 } // namespace vixl
|
| /external/vixl/test/aarch64/examples/ |
| test-examples.cc | 1 // Copyright 2015, VIXL authors
38 using namespace vixl;
39 using namespace vixl::aarch64;
|
| /external/vixl/test/ |
| test-pool-manager.cc | 1 // Copyright 2017, VIXL authors
42 using namespace vixl;
287 namespace vixl { namespace
[all...] |
| /art/compiler/optimizing/ |
| code_generator_arm_vixl.cc | 45 namespace vixl32 = vixl::aarch32;
72 using vixl::ExactAssemblyScope;
73 using vixl::CodeBufferCheckScope;
104 #error "ARM Codegen VIXL macro-assembler macro already defined."
150 // TODO: Maybe extend VIXL to allow ADR for return address?
186 // TODO(VIXL): All this code should be unnecessary once the VIXL AArch32 backend provides helpers
386 // TODO(VIXL): Check the coherency of stack_offset after this with a test.
[all...] |
| /external/vixl/src/aarch32/ |
| instructions-aarch32.h | 1 // Copyright 2017, VIXL authors
37 #include "code-buffer-vixl.h"
38 #include "utils-vixl.h"
47 namespace vixl { namespace
[all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | 1 // Copyright 2015, VIXL authors
30 #include "../assembler-base-vixl.h"
31 #include "../code-generation-scopes-vixl.h"
32 #include "../globals-vixl.h"
33 #include "../invalset-vixl.h"
34 #include "../utils-vixl.h"
38 namespace vixl { namespace
372 // Allow VIXL to generate code that refers to absolute addresses. With this
377 // Allow VIXL to assume that the bottom 12 bits of the address will be
404 class Assembler : public vixl::internal::AssemblerBase
[all...] |
