| /external/llvm/test/MC/ARM/ |
| ldr-pseudo-darwin.s | 7 @RUN: llvm-mc -triple armv7-base-apple-darwin %s | FileCheck --check-prefix=CHECK-ARM --check-prefix=CHECK %s
8 @RUN: llvm-mc -triple armv5-base-apple-darwin %s | FileCheck --check-prefix=CHECK-ARMV5 --check-prefix=CHECK %s
9 @RUN: llvm-mc -triple thumbv5-base-apple-darwin %s | FileCheck --check-prefix=CHECK-THUMB --check-prefix=CHECK %
[all...] |
| eh-directive-cantunwind.s | 4 @ Check the .cantunwind directive
24 @ Check .text section
26 @ CHECK: Sections [
27 @ CHECK: Section {
28 @ CHECK: Name: .text
29 @ CHECK: SectionData (
30 @ CHECK: 0000: 1EFF2FE1 |../.|
31 @ CHECK: )
32 @ CHECK: }
36 @ Check .ARM.exidx sectio
[all...] |
| directive-arch-armv8a.s | 3 @ This test case will check the default .ARM.attributes value for the
7 @ RUN: | FileCheck %s -check-prefix CHECK-ASM
9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
14 @ CHECK-ASM: .arch armv8-a
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 8-
[all...] |
| directive-arch-armv4t.s | 3 @ This test case will check the default .ARM.attributes value for the
7 @ RUN: | FileCheck %s -check-prefix CHECK-ASM
9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
14 @ CHECK-ASM: .arch armv4t
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 4
[all...] |
| directive-arch-armv5t.s | 3 @ This test case will check the default .ARM.attributes value for the
7 @ RUN: | FileCheck %s -check-prefix CHECK-ASM
9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
14 @ CHECK-ASM: .arch armv5t
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 5
[all...] |
| directive-arch-armv5te.s | 3 @ This test case will check the default .ARM.attributes value for the
7 @ RUN: | FileCheck %s -check-prefix CHECK-ASM
9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
14 @ CHECK-ASM: .arch armv5te
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 5T
[all...] |
| directive-arch-armv6.s | 3 @ This test case will check the default .ARM.attributes value for the
7 @ RUN: | FileCheck %s -check-prefix CHECK-ASM
9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
14 @ CHECK-ASM: .arch armv6
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value:
[all...] |
| directive-arch-armv6k.s | 3 @ This test case will check the default .ARM.attributes value for the
7 @ RUN: | FileCheck %s -check-prefix CHECK-ASM
9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
14 @ CHECK-ASM: .arch armv6k
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 6
[all...] |
| directive-arch-armv6t2.s | 3 @ This test case will check the default .ARM.attributes value for the
7 @ RUN: | FileCheck %s -check-prefix CHECK-ASM
9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
14 @ CHECK-ASM: .arch armv6t2
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 6T
[all...] |
| directive-arch-armv7-m.s | 3 @ This test case will check the default .ARM.attributes value for the
7 @ RUN: | FileCheck %s -check-prefix CHECK-ASM
9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
14 @ CHECK-ASM: .arch armv7-m
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 7-
[all...] |
| directive-arch-armv7m.s | 3 @ This test case will check the default .ARM.attributes value for the
7 @ RUN: | FileCheck %s -check-prefix CHECK-ASM
9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
14 @ CHECK-ASM: .arch armv7-m
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 7-
[all...] |
| eh-directive-personalityindex-diagnostics.s | 13 @ CHECK: error: .fnstart must precede .personalityindex directive
14 @ CHECK: .personalityindex 0
15 @ CHECK: ^
26 @ CHECK: error: .personalityindex cannot be used with .cantunwind
27 @ CHECK: .personalityindex 0
28 @ CHECK: ^
29 @ CHECK: note: .cantunwind was specified here
30 @ CHECK: .cantunwind
31 @ CHECK: ^
42 @ CHECK: error: .personalityindex must precede .handlerdata directiv
[all...] |
| directive-eabi_attribute-overwrite.s | 2 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
8 @ CHECK-ATTR: FileAttributes {
9 @ CHECK-ATTR: Attribute {
10 @ CHECK-ATTR: Value: 1, aeabi
11 @ CHECK-ATTR: TagName: compatibility
12 @ CHECK-ATTR: Description: AEABI Conformant
13 @ CHECK-ATTR: }
14 @ CHECK-ATTR: }
|
| /external/llvm/test/MC/Mips/ |
| micromips-relocations.s | 2 # RUN: -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
5 # RUN: | FileCheck %s -check-prefix=CHECK-ELF
7 # Check that the assembler can handle the documented syntax
10 # CHECK-FIXUP: lui $2, %hi(_gp_disp)
11 # CHECK-FIXUP: # encoding: [0xa2'A',0x41'A',0x00,0x00]
12 # CHECK-FIXUP: # fixup A - offset: 0,
13 # CHECK-FIXUP: value: %hi(_gp_disp),
14 # CHECK-FIXUP: kind: fixup_MICROMIPS_HI1
[all...] |
| branch-pseudos.s | 3 # RUN: FileCheck %s --check-prefix=WARNING
8 # CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a]
9 # CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A]
10 # CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
11 # CHECK: nop
13 # CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a]
14 # CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A]
15 # CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
16 # CHECK: nop
18 # CHECK: bltz $7, local_label # encoding: [0x04,0xe0,A,A
[all...] |
| /external/llvm/test/MC/PowerPC/ |
| ppc64-localentry.s | 42 # CHECK: ElfHeader {
43 # CHECK: Flags [ (0x2)
47 # CHECK: Relocations [
48 # CHECK: Section ({{[0-9]*}}) .rela.text {
49 # CHECK-NEXT: R_PPC64_REL24 callee1
50 # CHECK-NEXT: }
51 # CHECK-NOT: R_PPC64_REL24 callee2
52 # CHECK: Section ({{[0-9]*}}) .rela.text.other {
53 # CHECK-NEXT: R_PPC64_REL24 callee1
54 # CHECK-NEXT: R_PPC64_REL24 .tex
[all...] |
| ppc64-errors.s | 9 # CHECK: error: invalid operand for instruction
10 # CHECK-NEXT: add 32, 32, 32
13 # CHECK: error: invalid register name
14 # CHECK-NEXT: add %r32, %r32, %r32
19 # CHECK: error: invalid operand for instruction
20 # CHECK-NEXT: add 3, symbol@tls, 4
23 # CHECK: error: invalid operand for instruction
24 # CHECK-NEXT: subf 3, 4, symbol@tls
29 # CHECK: error: invalid operand for instruction
30 # CHECK-NEXT: addi 1, 0, -3276
[all...] |
| /external/llvm/test/tools/llvm-readobj/ARM/ |
| attribute-8.s | 3 @ RUN: | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=CHECK-OBJ
5 @CHECK: .eabi_attribute 6, 8
6 @CHECK-OBJ: Tag: 6
7 @CHECK-OBJ-NEXT: Value: 8
8 @CHECK-OBJ-NEXT: TagName: CPU_arch
9 @CHECK-OBJ-NEXT: Description: ARM v6T2
12 @CHECK: .eabi_attribute 10, 8
13 @CHECK-OBJ: Tag: 10
14 @CHECK-OBJ-NEXT: Value:
[all...] |
| /external/llvm/test/DebugInfo/X86/ |
| dbg-asm.s | 2 # RUN: | llvm-readobj -r - | FileCheck -check-prefix CHECK-COFF %s
4 # RUN: | llvm-readobj -r - | FileCheck -check-prefix CHECK-COFF %s
6 # RUN: | llvm-readobj -r - | FileCheck -check-prefix CHECK-ELF %s
12 # CHECK-COFF: Relocations [
13 # CHECK-COFF: Section {{.*}} .debug_info {
14 # CHECK-COFF: 0x6 IMAGE_REL_I386_SECREL .debug_abbrev
15 # CHECK-COFF: 0xC IMAGE_REL_I386_SECREL .debug_lin
[all...] |
| /external/dtc/tests/ |
| sw_tree1.c | 73 #define CHECK(code) \
117 CHECK(fdt_create(fdt, size));
121 CHECK(fdt_add_reservemap_entry(fdt, TEST_ADDR_1, TEST_SIZE_1));
123 CHECK(fdt_add_reservemap_entry(fdt, TEST_ADDR_2, TEST_SIZE_2));
124 CHECK(fdt_finish_reservemap(fdt));
126 CHECK(fdt_begin_node(fdt, ""));
127 CHECK(fdt_property_string(fdt, "compatible", "test_tree1"));
128 CHECK(fdt_property_u32(fdt, "prop-int", TEST_VALUE_1));
129 CHECK(fdt_property_u64(fdt, "prop-int64", TEST_VALUE64_1));
130 CHECK(fdt_property_string(fdt, "prop-str", TEST_STRING_1))
[all...] |
| /external/clang/test/CodeGenCXX/ |
| bitfield-layout.cpp | 1 // RUN: %clang_cc1 %s -triple=x86_64-apple-darwin10 -emit-llvm -o - -O3 | FileCheck -check-prefix CHECK-LP64 %s
2 // RUN: %clang_cc1 %s -triple=i386-apple-darwin10 -emit-llvm -o - -O3 | FileCheck -check-prefix CHECK-LP32 %s
4 // CHECK-LP64: %union.Test1 = type { i32, [4 x i8] }
10 // CHECK-LP64: %union.Test2 = type { i8 }
15 // CHECK-LP64: %union.Test3 = type { i16 }
21 #define CHECK(x) if (!(x)) return __LINE__
36 CHECK(c.a == 0);
37 CHECK(c.b == (unsigned long long)-1)
[all...] |
| /external/llvm/test/MC/AArch64/ |
| cyclone-crc.s | 7 CHECK: error: instruction requires: crc
8 CHECK: crc32b w0, w1, w5
9 CHECK: error: instruction requires: crc
10 CHECK: crc32h w3, w5, w6
11 CHECK: error: instruction requires: crc
12 CHECK: crc32w w19, wzr, w20
13 CHECK: error: instruction requires: crc
14 CHECK: crc32x w3, w5, x20
20 CHECK: error: instruction requires: crc
21 CHECK: crc32cb w5, w10, w1
[all...] |
| /external/llvm/test/MC/AsmParser/ |
| assignment.s | 3 # CHECK: TEST0:
4 # CHECK: a = 0
8 # CHECK: .globl _f1
9 # CHECK: _f1 = 0
|
| directive_comm.s | 3 # CHECK: TEST0:
4 # CHECK: .comm a,6,2
5 # CHECK: .comm b,8
6 # CHECK: .comm c,8
|
| directive_include.s | 3 # CHECK: TESTA:
4 # CHECK: TEST0:
5 # CHECK: a = 0
6 # CHECK: TESTB:
|
