| /external/llvm/lib/Target/Sparc/ |
| SparcTargetMachine.h | 30 StringRef FS, const TargetOptions &Options,
51 StringRef FS, const TargetOptions &Options,
62 StringRef FS, const TargetOptions &Options,
72 StringRef FS, const TargetOptions &Options,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetMachine.h | 31 StringRef FS, const TargetOptions &Options,
58 StringRef FS, const TargetOptions &Options,
69 StringRef FS, const TargetOptions &Options,
|
| AArch64Subtarget.cpp | 39 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
45 ParseSubtargetFeatures(CPUString, FS);
89 const std::string &FS,
91 : AArch64GenSubtargetInfo(TT, CPU, FS), ReserveX18(TT.isOSDarwin()),
93 InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
|
| /external/llvm/lib/Target/AVR/ |
| AVRTargetMachine.cpp | 42 StringRef CPU, StringRef FS,
48 getCPU(CPU), FS, Options, getEffectiveRelocModel(RM), CM, OL),
49 SubTarget(TT, getCPU(CPU), FS, *this) {
|
| /external/llvm/lib/Target/BPF/ |
| BPFTargetMachine.cpp | 47 StringRef CPU, StringRef FS,
51 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
54 Subtarget(TT, CPU, FS, *this) {
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430TargetMachine.cpp | 36 StringRef CPU, StringRef FS,
41 : LLVMTargetMachine(T, "e-m:e-p:16:16-i32:16:32-a:16-n8:16", TT, CPU, FS,
45 Subtarget(TT, CPU, FS, *this) {
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXSubtarget.h | 56 const std::string &FS, const NVPTXTargetMachine &TM);
102 NVPTXSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
103 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetMachine.h | 38 StringRef FS, const TargetOptions &Options,
67 StringRef FS, const TargetOptions &Options,
78 StringRef FS, const TargetOptions &Options,
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZSubtarget.h | 58 StringRef FS);
61 const std::string &FS, const TargetMachine &TM);
81 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreTargetMachine.cpp | 33 StringRef CPU, StringRef FS,
40 TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL),
42 Subtarget(TT, CPU, FS, *this) {
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUTargetMachine.cpp | 36 StringRef CPU, StringRef FS,
38 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
39 Subtarget(TT, CPU, FS),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXTargetMachine.h | 38 StringRef CPU, StringRef FS,
101 StringRef CPU, StringRef FS,
109 StringRef CPU, StringRef FS,
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCTargetMachine.h | 44 StringRef CPU, StringRef FS,
81 StringRef CPU, StringRef FS,
90 StringRef CPU, StringRef FS,
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcTargetMachine.h | 37 StringRef CPU, StringRef FS,
66 StringRef CPU, StringRef FS,
75 StringRef CPU, StringRef FS,
|
| /external/valgrind/none/tests/mips64/ |
| move_instructions.c | 92 /* movX.s fd, fs */
93 #define TEST3(instruction, FD, FS, cc, offset) \
102 "dmtc1 $zero, $"#FS "\n\t" \
105 "lwc1 $"#FS", "#offset"($t0)" "\n\t" \
110 : "t0", "t1", "$"#FD, "$"#FS, "$f0", "$f2" \
116 /* movX.d fd, fs */
117 #define TEST3d(instruction, FD, FS, cc, offset) \
128 "ldc1 $"#FS", "#offset"($t0)" "\n\t" \
133 : "t0", "t1", "$"#FD, "$"#FS, "$f0", "$f2" \
139 /* movX.s fd, fs, rt *
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCSubtargetInfo.h | 46 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
54 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
87 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
92 void setDefaultFeatures(StringRef CPU, StringRef FS);
104 FeatureBitset ToggleFeature(StringRef FS);
108 FeatureBitset ApplyFeatureFlag(StringRef FS);
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetMachine.cpp | 193 StringRef CPU, StringRef FS,
199 CPU, FS, Options, getEffectiveRelocModel(TT, RM), CM,
203 Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
231 std::string FS = !FSAttr.hasAttribute(Attribute::None)
245 FS += FS.empty() ? "+soft-float" : ",+soft-float";
247 auto &I = SubtargetMap[CPU + FS];
253 I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
267 StringRef CPU, StringRef FS,
272 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle)
[all...] |
| ARMSubtarget.cpp | 73 StringRef FS) {
75 initSubtargetFeatures(CPU, FS);
80 StringRef FS) {
81 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
89 const std::string &FS,
91 : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
93 TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
114 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
134 if (!FS.empty()) {
136 ArchFS = (Twine(ArchFS) + "," + FS).str()
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSubtarget.cpp | 67 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
85 ParseSubtargetFeatures(CPUString, FS);
96 StringRef FS, const TargetMachine &TM)
97 : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
98 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/MC/ |
| MCSubtargetInfo.h | 50 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
54 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
90 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
95 void setDefaultFeatures(StringRef CPU, StringRef FS);
107 FeatureBitset ToggleFeature(StringRef FS);
111 FeatureBitset ApplyFeatureFlag(StringRef FS);
|
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/MC/ |
| MCSubtargetInfo.h | 53 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
57 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
98 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
103 void setDefaultFeatures(StringRef CPU, StringRef FS);
115 FeatureBitset ToggleFeature(StringRef FS);
119 FeatureBitset ApplyFeatureFlag(StringRef FS);
|
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/MC/ |
| MCSubtargetInfo.h | 53 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
57 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
98 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
103 void setDefaultFeatures(StringRef CPU, StringRef FS);
115 FeatureBitset ToggleFeature(StringRef FS);
119 FeatureBitset ApplyFeatureFlag(StringRef FS);
|
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/MC/ |
| MCSubtargetInfo.h | 50 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
54 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
90 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
95 void setDefaultFeatures(StringRef CPU, StringRef FS);
107 FeatureBitset ToggleFeature(StringRef FS);
111 FeatureBitset ApplyFeatureFlag(StringRef FS);
|
| /prebuilts/clang/host/linux-x86/clang-4393122/include/llvm/MC/ |
| MCSubtargetInfo.h | 53 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
57 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
98 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
103 void setDefaultFeatures(StringRef CPU, StringRef FS);
115 FeatureBitset ToggleFeature(StringRef FS);
119 FeatureBitset ApplyFeatureFlag(StringRef FS);
|
| /prebuilts/clang/host/linux-x86/clang-4479392/include/llvm/MC/ |
| MCSubtargetInfo.h | 53 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
57 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
98 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
103 void setDefaultFeatures(StringRef CPU, StringRef FS);
115 FeatureBitset ToggleFeature(StringRef FS);
119 FeatureBitset ApplyFeatureFlag(StringRef FS);
|
