| /external/apache-http/src/org/apache/commons/logging/ |
| LogFactory.java | 515 BufferedReader rd; local
517 rd = new BufferedReader(new InputStreamReader(is, "UTF-8"));
519 rd = new BufferedReader(new InputStreamReader(is));
522 String factoryClassName = rd.readLine();
523 rd.close();
[all...] |
| /external/ltp/utils/ffsb-6.0-rc2/ |
| ffsb_fs.c | 88 randdata_t rd; local
99 init_random(&rd, 0);
120 int num = 1 + getrandom(&rd, fs->sum_weights);
129 size = minsize + getllrandom(&rd, maxsize - minsize);
131 cur = add_file(bf, size, &rd);
|
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-operand-rn-t32.cc | 80 Register rd; member in struct:vixl::aarch32::__anon43314::Operands
336 #include "aarch32/traces/assembler-cond-rd-operand-rn-cmn-t32.h"
337 #include "aarch32/traces/assembler-cond-rd-operand-rn-cmp-t32.h"
338 #include "aarch32/traces/assembler-cond-rd-operand-rn-mov-t32.h"
339 #include "aarch32/traces/assembler-cond-rd-operand-rn-movs-t32.h"
340 #include "aarch32/traces/assembler-cond-rd-operand-rn-mvn-t32.h"
341 #include "aarch32/traces/assembler-cond-rd-operand-rn-mvns-t32.h"
342 #include "aarch32/traces/assembler-cond-rd-operand-rn-sxtb-t32.h"
343 #include "aarch32/traces/assembler-cond-rd-operand-rn-sxtb16-t32.h"
344 #include "aarch32/traces/assembler-cond-rd-operand-rn-sxth-t32.h
370 Register rd = kTests[i].operands.rd; local
[all...] |
| test-assembler-cond-rd-rn-t32.cc | 73 Register rd; member in struct:vixl::aarch32::__anon43337::Operands
329 #include "aarch32/traces/assembler-cond-rd-rn-clz-t32.h"
330 #include "aarch32/traces/assembler-cond-rd-rn-rbit-t32.h"
331 #include "aarch32/traces/assembler-cond-rd-rn-rev-t32.h"
332 #include "aarch32/traces/assembler-cond-rd-rn-rev16-t32.h"
333 #include "aarch32/traces/assembler-cond-rd-rn-revsh-t32.h"
334 #include "aarch32/traces/assembler-cond-rd-rn-rrx-t32.h"
335 #include "aarch32/traces/assembler-cond-rd-rn-rrxs-t32.h"
341 typedef void (MacroAssembler::*Fn)(Condition cond, Register rd, Register rn);
354 Register rd = kTests[i].operands.rd local
[all...] |
| test-assembler-cond-sp-sp-operand-imm7-t32.cc | 68 Register rd; member in struct:vixl::aarch32::__anon43349::Operands
236 Register rd,
251 Register rd = kTests[i].operands.rd; local
264 (masm.*instruction)(cond, rd, rn, op);
|
| test-simulator-cond-rd-operand-rn-shift-rs-a32.cc | 139 Register rd; member in struct:vixl::aarch32::__anon43373::Operands
148 uint32_t rd; member in struct:vixl::aarch32::__anon43373::Inputs
1096 Register rd = kTests[i].operands.rd; local
1195 uint32_t rd = results[i]->outputs[j].rd; local
[all...] |
| test-simulator-cond-rd-operand-rn-shift-rs-t32.cc | 133 Register rd; member in struct:vixl::aarch32::__anon43374::Operands
142 uint32_t rd; member in struct:vixl::aarch32::__anon43374::Inputs
1084 Register rd = kTests[i].operands.rd; local
1183 uint32_t rd = results[i]->outputs[j].rd; local
[all...] |
| test-simulator-cond-rd-rn-a32.cc | 138 Register rd; member in struct:vixl::aarch32::__anon43376::Operands
145 uint32_t rd; member in struct:vixl::aarch32::__anon43376::Inputs
881 Register rd = kTests[i].operands.rd; local
972 uint32_t rd = results[i]->outputs[j].rd; local
[all...] |
| test-simulator-cond-rd-rn-operand-const-a32.cc | 151 Register rd; member in struct:vixl::aarch32::__anon43377::Operands
159 uint32_t rd; member in struct:vixl::aarch32::__anon43377::Inputs
1129 Register rd = kTests[i].operands.rd; local
1222 uint32_t rd = results[i]->outputs[j].rd; local
[all...] |
| test-simulator-cond-rd-rn-operand-const-t32.cc | 151 Register rd; member in struct:vixl::aarch32::__anon43378::Operands
159 uint32_t rd; member in struct:vixl::aarch32::__anon43378::Inputs
1153 Register rd = kTests[i].operands.rd; local
1246 uint32_t rd = results[i]->outputs[j].rd; local
[all...] |
| test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc | 137 Register rd; member in struct:vixl::aarch32::__anon43381::Operands
147 uint32_t rd; member in struct:vixl::aarch32::__anon43381::Inputs
1128 Register rd = kTests[i].operands.rd; local
1228 uint32_t rd = results[i]->outputs[j].rd; local
[all...] |
| test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc | 137 Register rd; member in struct:vixl::aarch32::__anon43382::Operands
147 uint32_t rd; member in struct:vixl::aarch32::__anon43382::Inputs
1128 Register rd = kTests[i].operands.rd; local
1228 uint32_t rd = results[i]->outputs[j].rd; local
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 151 Register rd; member in struct:vixl::aarch32::__anon43383::Operands
161 uint32_t rd; member in struct:vixl::aarch32::__anon43383::Inputs
1446 Register rd = kTests[i].operands.rd; local
1546 uint32_t rd = results[i]->outputs[j].rd; local
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 151 Register rd; member in struct:vixl::aarch32::__anon43384::Operands
161 uint32_t rd; member in struct:vixl::aarch32::__anon43384::Inputs
1446 Register rd = kTests[i].operands.rd; local
1546 uint32_t rd = results[i]->outputs[j].rd; local
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 151 Register rd; member in struct:vixl::aarch32::__anon43385::Operands
161 uint32_t rd; member in struct:vixl::aarch32::__anon43385::Inputs
1456 Register rd = kTests[i].operands.rd; local
1556 uint32_t rd = results[i]->outputs[j].rd; local
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 151 Register rd; member in struct:vixl::aarch32::__anon43386::Operands
161 uint32_t rd; member in struct:vixl::aarch32::__anon43386::Inputs
1456 Register rd = kTests[i].operands.rd; local
1556 uint32_t rd = results[i]->outputs[j].rd; local
[all...] |
| test-simulator-cond-rd-rn-t32.cc | 138 Register rd; member in struct:vixl::aarch32::__anon43397::Operands
145 uint32_t rd; member in struct:vixl::aarch32::__anon43397::Inputs
881 Register rd = kTests[i].operands.rd; local
972 uint32_t rd = results[i]->outputs[j].rd; local
[all...] |
| test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc | 137 Register rd; member in struct:vixl::aarch32::__anon43399::Operands
145 uint32_t rd; member in struct:vixl::aarch32::__anon43399::Inputs
982 Register rd = kTests[i].operands.rd; local
1075 uint32_t rd = results[i]->outputs[j].rd; local
[all...] |
| /external/llvm/test/MC/Sparc/ |
| sparc-synthetic-instructions.s | 113 ! CHECK: rd %y, %i0 ! encoding: [0xb1,0x40,0x00,0x00]
115 ! CHECK: rd %asr1, %i0 ! encoding: [0xb1,0x40,0x40,0x00]
117 ! CHECK: rd %psr, %i0 ! encoding: [0xb1,0x48,0x00,0x00]
119 ! CHECK: rd %wim, %i0 ! encoding: [0xb1,0x50,0x00,0x00]
121 ! CHECK: rd %tbr, %i0 ! encoding: [0xb1,0x58,0x00,0x00]
|
| /external/llvm/test/MC/X86/ |
| avx512-encodings.s | [all...] |
| /external/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 381 unsigned rd = fieldFromInstruction(insn, 25, 5); local
395 status = DecodeRD(MI, rd, Address, Decoder);
418 status = DecodeRD(MI, rd, Address, Decoder);
538 unsigned rd = fieldFromInstruction(insn, 25, 5); local
548 // Decode RD.
549 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
600 unsigned rd = fieldFromInstruction(insn, 25, 5); local
612 // Decode RD.
613 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
|
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| nv50_ir_emit_nvc0.cpp | 405 if ((s == 2) && ((code[0] & 0x7) == 2)) // LIMM: 3rd src == dst
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/i386/ |
| x86-64-evex-lig256-intel.d | 16 [ ]*[a-f0-9]+: 62 01 97 37 58 f4 vaddsd xmm30\{k7\},xmm29,xmm28,\{rd-sae\}
28 [ ]*[a-f0-9]+: 62 01 16 37 58 f4 vaddss xmm30\{k7\},xmm29,xmm28,\{rd-sae\}
[all...] |
| x86-64-evex-lig256.d | 16 [ ]*[a-f0-9]+: 62 01 97 37 58 f4 vaddsd \{rd-sae\},%xmm28,%xmm29,%xmm30\{%k7\}
28 [ ]*[a-f0-9]+: 62 01 16 37 58 f4 vaddss \{rd-sae\},%xmm28,%xmm29,%xmm30\{%k7\}
[all...] |
| x86-64-evex-lig512-intel.d | 16 [ ]*[a-f0-9]+: 62 01 97 37 58 f4 vaddsd xmm30\{k7\},xmm29,xmm28,\{rd-sae\}
28 [ ]*[a-f0-9]+: 62 01 16 37 58 f4 vaddss xmm30\{k7\},xmm29,xmm28,\{rd-sae\}
[all...] |
