| /device/linaro/bootloader/arm-trusted-firmware/bl31/aarch64/ |
| crash_reporting.S | 32 .asciz "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\
80 /* Calculate x5 always as it will be clobbered by asm_print_hex */
81 mrs x5, tpidr_el3
82 add x5, x5, #CPU_DATA_CRASH_BUF_SIZE
84 cmp x7, x5
219 stp x4, x5, [x0, #REG_SIZE * 4]
|
| /external/clang/test/FixIt/ |
| fixit.cpp | 79 int x5 != 0; // expected-error {{invalid '!=' at end of declaration; did you mean '='?}} member in namespace:rdar8488464
101 int x5 != 0; // expected-error {{invalid '!=' at end of declaration; did you mean '='?}} local
102 (void)x5;
126 if (int x5 != 0) { (void)x5; } // expected-error {{invalid '!=' at end of declaration; did you mean '='?}}
|
| /external/llvm/test/MC/COFF/ |
| seh-section-2.s | 78 # CHECK: Selection: Associative (0x5)
96 # CHECK: Selection: Associative (0x5)
114 # CHECK: Selection: Associative (0x5)
132 # CHECK: Selection: Associative (0x5)
150 # CHECK: Selection: Associative (0x5)
|
| /external/libhevc/common/arm64/ |
| ihevc_sao_edge_offset_class0_chroma.s | 59 //x5 => *pi1_sao_offset_v
86 mov x16,x5 // *pu1_src_top_right 44
117 MOV x5, x23 //Loads pi1_sao_offset_v
133 LD1 {v0.8b},[x5] //offset_tbl = vld1_s8(pi1_sao_offset_v)
168 SUB x5,x9,x8 //wd - col
182 ADD x5,x14,x5 //(ht - row) * src_strd + (wd - col)
187 LDRH w14,[x6,x5] //pu1_src_org[(ht - row) * src_strd + 14 + (wd - col)]
280 SUB x5,x9,x8 //II wd - col
286 ADD x5,x14,x5 //II (ht - row) * src_strd + (wd - col
[all...] |
| /external/llvm/test/MC/AArch64/ |
| basic-a64-instructions.s | 25 add x3, x5, x9, sxtx
33 // CHECK: add x3, x5, x9, sxtx // encoding: [0xa3,0xe0,0x29,0x8b]
71 sub x3, x5, x9, sxtx
79 // CHECK: sub x3, x5, x9, sxtx // encoding: [0xa3,0xe0,0x29,0xcb]
106 adds x3, x5, x9, sxtx #2
114 // CHECK: adds x3, x5, x9, sxtx #2 // encoding: [0xa3,0xe8,0x29,0xab]
141 subs x3, x5, x9, sxtx #2
149 // CHECK: subs x3, x5, x9, sxtx #2 // encoding: [0xa3,0xe8,0x29,0xeb]
176 cmp x5, x9, sxtx #2
184 // CHECK: cmp x5, x9, sxtx #2 // encoding: [0xbf,0xe8,0x29,0xeb
[all...] |
| arm64-aliases.s | 15 mov x5, sp
16 ; CHECK: mov x5, sp
67 cmn x4, x5, uxtx #1
76 ; CHECK: cmn x4, x5, uxtx #1 ; encoding: [0x9f,0x64,0x25,0xab]
89 cmp x4, x5, uxtx
102 ; CHECK: cmp x4, x5, uxtx ; encoding: [0x9f,0x60,0x25,0xeb]
212 orr x5, xzr, #0xfffffffffffffff0
214 orr x5, xzr, #0xfffffffffcffffff
216 orr x5, xzr, #0xffffff00ffffffff
217 orr x5, xzr, #0x8000fffffffffff
[all...] |
| tls-relocs.s | 28 movz x5, #:dtprel_g1:var
33 // CHECK: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
230 movz x5, #:tprel_g1:var
235 // CHECK: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
379 add x5, x4, #:tlsdesc_lo12:var
388 // CHECK: add x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91]
|
| /external/llvm/test/MC/ARM/ |
| thumb_set.s | 80 @ CHECK: Value: 0x5
86 @ CHECK: Value: 0x5
150 @ CHECK: Value: 0x5
|
| /external/mesa3d/src/mesa/drivers/dri/nouveau/ |
| nv04_state_raster.c | 48 return 0x5;
73 return 0x5;
98 return 0x5;
|
| /external/pdfium/third_party/libtiff/ |
| t4.h | 105 { 8, 0x5, 46 }, /* 0000 0101 */
179 { 6, 0x5, 8 }, /* 0001 01 */
182 { 7, 0x5, 11 }, /* 0000 101 */
|
| /external/strace/xlat/ |
| quotacmds.h | 15 # define Q_V1_SETUSE OLD_CMD(0x5)
66 # define Q_GETINFO NEW_CMD(0x5)
93 # define Q_XGETQSTAT XQM_CMD(0x5)
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| reloc-insn.d | 54 88: 10000005 adr x5, 0 <xdata>
66 a0: 90000005 adrp x5, 0 <xdata>
78 b8: 90000005 adrp x5, 0 <xdata>
90 d0: 910000a5 add x5, x5, #0x0
103 ec: 394000a5 ldrb w5, \[x5\]
|
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-i386/ |
| compressed1.s | 54 .byte 0x5
58 .byte 0x5
62 .byte 0x5
|
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-x86-64/ |
| compressed1.s | 44 .byte 0x5
48 .byte 0x5
52 .byte 0x5
|
| /device/linaro/bootloader/arm-trusted-firmware/include/lib/el3_runtime/aarch64/ |
| context.h | 295 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \
296 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \
299 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \
301 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \
303 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \
305 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmExceptionLib/AArch64/ |
| ExceptionSupport.S | 30 UINT64 X5; 0x028
132 stp x4, x5, [sp, #0x20]
138 mrs x5, esr_el1 // EL1 Exception syndrome register 32bit
144 mrs x5, esr_el2 // EL2 Exception syndrome register 32bit
150 mrs x5, esr_el3 // EL3 Exception syndrome register 32bit
268 stp x4, x5, [x28, #0x10]
306 ldp x4, x5, [sp, #0x20]
|
| /prebuilts/go/darwin-x86/src/runtime/ |
| defs1_netbsd_386.go | 29 _SIGTRAP = 0x5
61 _FPE_FLTUND = 0x5
164 _REG_ESI = 0x5
|
| defs1_netbsd_arm.go | 29 _SIGTRAP = 0x5
61 _FPE_FLTUND = 0x5
171 _REG_R5 = 0x5
|
| defs_freebsd_arm.go | 28 _MADV_FREE = 0x5
45 _SIGTRAP = 0x5
77 _FPE_FLTUND = 0x5
|
| /prebuilts/go/linux-x86/src/runtime/ |
| defs1_netbsd_386.go | 29 _SIGTRAP = 0x5
61 _FPE_FLTUND = 0x5
164 _REG_ESI = 0x5
|
| defs1_netbsd_arm.go | 29 _SIGTRAP = 0x5
61 _FPE_FLTUND = 0x5
171 _REG_R5 = 0x5
|
| defs_freebsd_arm.go | 28 _MADV_FREE = 0x5
45 _SIGTRAP = 0x5
77 _FPE_FLTUND = 0x5
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/m68hc11/ |
| lbranch.d | 14 0+0005 <_rcall\+0x5> jsr 0x0+0+ <_rcall>
66 0+010b <Lend> bls 0x0+0110 <Lend\+0x5>
70 0+0110 <Lend\+0x5> bhi 0x0+0115 <Lend\+0xa>
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/ |
| D05Mcfg.aslc | 75 0x5, //Segment Group Number
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/common/aarch64/ |
| plat_helpers.S | 156 adr x5, cpuson_entry_point
157 ldr x2, [x5, x21, lsl #3]
|
