| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 291 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
351 if (Use->getOpcode() == ISD::CopyToReg)
447 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
449 if (N.getOpcode() == ISD::FrameIndex) {
459 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
469 if (N.getOpcode() == ISD::SUB)
474 if (Base.getOpcode() == ISD::FrameIndex) {
493 if (N.getOpcode() == ISD::MUL &&
517 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &
[all...] |
| ARMCallingConv.h | 61 ISD::ArgFlagsTy &ArgFlags,
109 ISD::ArgFlagsTy &ArgFlags,
141 ISD::ArgFlagsTy &ArgFlags,
152 ISD::ArgFlagsTy &ArgFlags,
|
| /external/llvm/lib/Target/Mips/ |
| MipsCCState.cpp | 75 const SmallVectorImpl<ISD::InputArg> &Ins,
87 const SmallVectorImpl<ISD::OutputArg> &Outs) {
100 const SmallVectorImpl<ISD::OutputArg> &Outs,
115 const SmallVectorImpl<ISD::InputArg> &Ins) {
|
| MipsISelLowering.h | 31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
202 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
241 ISD::NodeType getExtendForAtomicOps() const override {
242 return ISD::SIGN_EXTEND;
262 /// getSetCCResultType - get the ISD::SETCC result ValueType
319 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
346 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
362 return DAG.getNode(ISD::ADD, DL, Ty,
376 return DAG.getNode(ISD::ADD, DL, Ty
[all...] |
| MipsSEISelDAGToDAG.cpp | 245 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
246 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
335 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
336 Addr.getOpcode() == ISD::TargetGlobalAddress))
345 if (Addr.getOpcode() == ISD::ADD) {
496 // * N is a ISD::BUILD_VECTOR representing a constant splat
528 // This function looks through ISD::BITCAST nodes.
542 if (N->getOpcode() == ISD::BITCAST
[all...] |
| MipsISelDAGToDAG.cpp | 218 case ISD::GLOBAL_OFFSET_TABLE:
223 case ISD::LOAD:
224 case ISD::STORE:
|
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 315 if (User->getOpcode() == ISD::STORE &&
335 User->getOpcode() == ISD::ADD ||
337 User->getOpcode() == ISD::SUB) {
346 if (OtherOp->getOpcode() == ISD::CopyFromReg &&
406 if (N.getOpcode() != ISD::LOAD)
418 case ISD::ADD:
419 case ISD::ADDC:
420 case ISD::ADDE:
421 case ISD::AND:
422 case ISD::OR
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZSelectionDAGInfo.cpp | 105 Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
110 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2);
119 SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
124 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2);
139 SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
176 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
178 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,
205 Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char,
207 SDValue Limit = DAG.getNode(ISD::ADD, DL, PtrVT, Src, Length);
260 SDValue Len = DAG.getNode(ISD::SUB, DL, PtrVT, End, Src)
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.h | 109 /// from the LLVM IR Function and fixup the ISD:InputArg values before
113 const SmallVectorImpl<ISD::InputArg> &Ins,
114 SmallVectorImpl<ISD::InputArg> &OrigIns) const;
116 const SmallVectorImpl<ISD::InputArg> &Ins) const;
118 const SmallVectorImpl<ISD::OutputArg> &Outs) const;
140 ISD::LoadExtType ExtType,
153 const SmallVectorImpl<ISD::OutputArg> &Outs,
220 // AMDIL ISD Opcodes
221 FIRST_NUMBER = ISD::BUILTIN_OP_END,
225 // End AMDIL ISD Opcode
[all...] |
| AMDGPUISelDAGToDAG.cpp | 42 assert(N->getOpcode() == ISD::BRCOND);
47 if (Cond.getOpcode() == ISD::CopyToReg)
49 return Cond.getOpcode() == ISD::SETCC &&
277 case ISD::ADD:
278 case ISD::SUB: {
286 case ISD::SCALAR_TO_VECTOR:
288 case ISD::BUILD_VECTOR: {
347 assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
363 case ISD::BUILD_PAIR: {
387 case ISD::Constant
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetTransformInfo.cpp | 317 int ISD = TLI->InstructionOpcodeToISD(Opcode);
318 assert(ISD && "Invalid opcode");
339 if (ISD == ISD::INSERT_VECTOR_ELT)
346 if (ISD == ISD::EXTRACT_VECTOR_ELT ||
347 ISD == ISD::INSERT_VECTOR_ELT)
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 215 Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
228 Reg = fastEmit_f(VT, VT, ISD::ConstantFP, CF);
246 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg,
329 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN,
334 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN, IdxNIsKill);
398 if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
399 ISDOpcode == ISD::XOR))
435 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
438 ISDOpcode = ISD::SRA
[all...] |
| ResourcePriorityQueue.cpp | 87 case ISD::TokenFactor: break;
88 case ISD::CopyFromReg: NumberDeps++; break;
89 case ISD::CopyToReg: break;
90 case ISD::INLINEASM: break;
124 case ISD::TokenFactor: break;
125 case ISD::CopyFromReg: break;
126 case ISD::CopyToReg: NumberDeps++; break;
127 case ISD::INLINEASM: break;
455 case ISD::TokenFactor:
456 case ISD::CopyFromReg
[all...] |
| SelectionDAGBuilder.h | 219 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
229 ISD::CondCode CC;
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 145 static ISD::NodeType getExtendForContent(BooleanContent Content) {
149 return ISD::ANY_EXTEND;
152 return ISD::ZERO_EXTEND;
155 return ISD::SIGN_EXTEND;
187 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
188 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
286 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
287 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Target/ |
| TargetLowering.h | 196 static ISD::NodeType getExtendForContent(BooleanContent Content) {
200 return ISD::ANY_EXTEND;
203 return ISD::ZERO_EXTEND;
206 return ISD::SIGN_EXTEND;
240 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
241 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
371 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
372 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Target/ |
| TargetLowering.h | 196 static ISD::NodeType getExtendForContent(BooleanContent Content) {
200 return ISD::ANY_EXTEND;
203 return ISD::ZERO_EXTEND;
206 return ISD::SIGN_EXTEND;
240 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
241 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
371 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
372 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelLowering.h | 32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
318 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
590 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
752 const SmallVectorImpl<ISD::InputArg> &Ins,
757 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
764 ISD::ArgFlagsTy Flags) const;
776 const SmallVectorImpl<ISD::OutputArg> &Outs,
778 const SmallVectorImpl<ISD::InputArg> &Ins,
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 30 OP_BEGIN = ISD::BUILTIN_OP_END,
110 bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
112 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
136 const SmallVectorImpl<ISD::InputArg> &Ins,
157 const SmallVectorImpl<ISD::InputArg> &Ins,
172 const SmallVectorImpl<ISD::OutputArg> &Outs,
208 ISD::MemIndexedMode &AM,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 95 if (Addr.getOpcode() == ISD::ADD) {
136 case ISD::Constant: {
204 case ISD::BRIND:
222 if (Chain->getOpcode() != ISD::TokenFactor)
236 return CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, Ops);
244 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
275 nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 195 case ISD::Constant: {
208 case ISD::FrameIndex:
217 case ISD::SUB: {
248 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
265 case ISD::ADD: {
289 case ISD::OR:
368 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
376 if (UI->getOpcode() == ISD::CopyToReg) {
417 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
193 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
251 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
312 ISD::MemIndexedMode &AM,
319 SDValue &Offset, ISD::MemIndexedMode &AM,
514 ISD::ArgFlagsTy Flags) const;
526 ISD::ArgFlagsTy Flags) const;
592 const SmallVectorImpl<ISD::InputArg> &Ins,
608 const SmallVectorImpl<ISD::InputArg> &Ins,
637 const SmallVectorImpl<ISD::OutputArg> &Outs
[all...] |
| ARMSelectionDAGInfo.cpp | 92 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
94 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
213 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
222 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
237 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
244 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64CallingConvention.h | 45 MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
67 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
86 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
|
| AArch64ISelLowering.h | 30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
93 // Vector bit select: similar to ISD::VSELECT but not all bits within an
180 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
195 LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
273 /// Return the ISD::SETCC ValueType.
430 const SmallVectorImpl<ISD::InputArg> &Ins,
439 const SmallVectorImpl<ISD::InputArg> &Ins,
448 const SmallVectorImpl<ISD::OutputArg> &Outs,
450 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
467 const SmallVectorImpl<ISD::OutputArg> &Outs
[all...] |
