| /external/vixl/test/aarch32/ |
| test-simulator-cond-rd-operand-rn-a32.cc | 118 M(Mov) \
477 #include "aarch32/traces/simulator-cond-rd-operand-rn-mov-a32.h"
545 __ Mov(input_ptr, Operand::From(kTests[i].inputs));
547 __ Mov(result_ptr, Operand::From(results[i]->outputs));
|
| test-simulator-cond-rd-operand-rn-t32.cc | 118 M(Mov) \
477 #include "aarch32/traces/simulator-cond-rd-operand-rn-mov-t32.h"
545 __ Mov(input_ptr, Operand::From(kTests[i].inputs));
547 __ Mov(result_ptr, Operand::From(results[i]->outputs));
|
| test-simulator-cond-rd-memop-immediate-512-a32.cc | [all...] |
| test-simulator-cond-rd-memop-immediate-8192-a32.cc | [all...] |
| test-simulator-cond-rd-memop-rs-a32.cc | [all...] |
| test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc | [all...] |
| test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc | [all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 118 M(Mov) \
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 118 M(Mov) \
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 118 M(Mov) \
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 118 M(Mov) \
[all...] |
| test-simulator-cond-rdlow-operand-imm8-t32.cc | 117 M(Mov) \
[all...] |
| test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 610 __ Mov(input_ptr, Operand::From(kTests[i].inputs));
612 __ Mov(result_ptr, Operand::From(results[i]->outputs));
[all...] |
| test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 610 __ Mov(input_ptr, Operand::From(kTests[i].inputs));
612 __ Mov(result_ptr, Operand::From(results[i]->outputs));
[all...] |
| test-simulator-rd-rn-rm-a32.cc | 516 __ Mov(input_ptr, Operand::From(kTests[i].inputs));
518 __ Mov(result_ptr, Operand::From(results[i]->outputs));
|
| test-simulator-rd-rn-rm-t32.cc | 516 __ Mov(input_ptr, Operand::From(kTests[i].inputs));
518 __ Mov(result_ptr, Operand::From(results[i]->outputs));
|
| /art/compiler/optimizing/ |
| intrinsics_arm64.cc | 91 __ Mov(trg_reg, res_reg, kDiscardForSameWReg);
482 __ Mov(dst, UINT64_C(1) << high_bit); // MOV (bitmask immediate)
[all...] |
| code_generator_vector_arm64.cc | [all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.h | 636 // instruction using 'mov immediate' instructions. A user might prefer loading
637 // a constant using the literal pool instead of using multiple 'mov immediate'
698 void Mov(const Register& rd, uint64_t imm);
699 void Mov(const Register& rd,
703 Mov(rd, (rd.GetSizeInBits() == kXRegSize) ? ~imm : (~imm & kWRegMask));
[all...] |
| /external/libxaac/decoder/armv7/ |
| ixheaacd_sbr_qmfanal32_winadds_eld.s | 12 MOV R9, R7, LSL #1
15 MOV r10, #3
47 MOV R5, #8
50 MOV R6, #64
51 MOV R6, R6, LSL #1 @
54 MOV R7, #244 @ NOT USED further
56 MOV R9, R0
59 MOV R11, R4 @ Mov winAdd to R11
64 MOV R10, R2
[all...] |
| /external/v8/src/interpreter/ |
| bytecode-register-optimizer.cc | 277 BytecodeNode node = BytecodeNode::Mov(source_info, operand0, operand1);
|
| /art/compiler/linker/arm64/ |
| relative_patcher_arm64.cc | 473 __ Mov(ip0, base_reg); // Move the base register to ip0.
502 __ Mov(ip0.W(), root_reg);
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 544 MachineInstrBuilder Mov
556 Mov.addReg(SuperReg, RegState::Implicit | SuperKillState);
[all...] |
| /external/valgrind/VEX/priv/ |
| host_arm_defs.c | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 818 MachineInstrBuilder Mov;
836 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
839 Mov.addReg(Src);
840 Mov = AddDefaultPred(Mov);
843 Mov = AddDefaultCC(Mov);
846 Mov->addRegisterDefined(DestReg, TRI);
848 Mov->addRegisterKilled(SrcReg, TRI);
[all...] |
