| /external/llvm/lib/CodeGen/ |
| RegAllocBase.h | 93 /// enqueue - Add VirtReg to the priority queue of unassigned registers.
103 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
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| VirtRegMap.cpp | 82 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
83 unsigned Hint = MRI->getSimpleHint(VirtReg);
88 return getPhys(VirtReg) == Hint;
91 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
92 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
100 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
101 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
102 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
104 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
105 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC)
[all...] |
| LiveDebugVariables.cpp | 310 /// lookupVirtReg - Find the EC leader for VirtReg or null.
311 UserValue *lookupVirtReg(unsigned VirtReg);
349 void mapVirtReg(unsigned VirtReg, UserValue *EC);
479 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) {
480 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs");
481 UserValue *&Leader = virtRegToEqClass[VirtReg];
485 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) {
486 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
923 unsigned VirtReg = Loc.getReg();
924 if (VRM.isAssignedReg(VirtReg) &
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 89 void unify(LiveInterval &VirtReg, const LiveRange &Range);
92 void extract(LiveInterval &VirtReg, const LiveRange &Range);
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| ScheduleDAGInstrs.h | 36 unsigned VirtReg;
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
44 return TargetRegisterInfo::virtReg2Index(VirtReg);
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| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
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| ScheduleDAGInstrs.h | 53 unsigned VirtReg;
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
61 return TargetRegisterInfo::virtReg2Index(VirtReg);
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| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
|
| ScheduleDAGInstrs.h | 53 unsigned VirtReg;
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
61 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
|
| ScheduleDAGInstrs.h | 53 unsigned VirtReg;
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
61 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
| /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
|
| ScheduleDAGInstrs.h | 53 unsigned VirtReg;
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
61 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
| /prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
|
| /prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
|
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 89 void unify(LiveInterval &VirtReg, const LiveRange &Range);
92 void extract(LiveInterval &VirtReg, const LiveRange &Range);
|
| /prebuilts/clang/host/linux-x86/clang-4393122/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
|
| /prebuilts/clang/host/linux-x86/clang-4479392/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
|
| /prebuilts/clang/host/linux-x86/clang-4579689/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
|
| /prebuilts/clang/host/linux-x86/clang-4630689/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
|
| /prebuilts/clang/host/linux-x86/clang-4639204/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
|
| /prebuilts/clang/host/linux-x86/clang-4691093/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| LiveDebugVariables.cpp | 303 /// lookupVirtReg - Find the EC leader for VirtReg or null.
304 UserValue *lookupVirtReg(unsigned VirtReg);
335 void mapVirtReg(unsigned VirtReg, UserValue *EC);
429 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) {
430 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs");
431 UserValue *&Leader = virtRegToEqClass[VirtReg];
435 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) {
436 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
885 unsigned VirtReg = Loc.getReg();
886 if (VRM.isAssignedReg(VirtReg) &
[all...] |
| VirtRegMap.cpp | 118 unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
119 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(virtReg);
129 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
130 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
131 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
133 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
134 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
137 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
138 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
139 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 36 unsigned VirtReg;
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
44 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
