| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_tgsi_vgpu10.c | 443 * writes we need to mask the declaration usage or instruction writemask
451 * declaration or instruction writemask.
453 * \param writemask the declaration usage mask or instruction writemask
460 unsigned writemask, unsigned clip_reg_index)
468 writemask &= ((emit->key.clip_plane_enable >> shift) & 0xf);
470 return writemask;
856 unsigned writemask = reg->Register.WriteMask; local
932 /* the operand has a writemask */
2536 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_ALL; local
3273 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_X << comp; local
3315 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_X << comp; local
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| r300_fragprog_emit.c | 246 if (inst->RGB.WriteMask) {
252 (inst->RGB.WriteMask << R300_ALU_DSTC_REG_MASK_SHIFT);
261 if (inst->Alpha.WriteMask) {
|
| r500_fragprog.c | 109 inst_mov->U.I.DstReg.WriteMask = 0;
159 writer->Inst->U.I.DstReg.WriteMask = 0;
|
| radeon_dataflow_swizzles.c | 63 mov->U.I.DstReg.WriteMask = split.Phase[phase];
|
| radeon_vert_fc.c | 56 dst->WriteMask = RC_MASK_W;
|
| r500_fragprog_emit.c | 269 code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11);
270 code->inst[ip].inst0 |= inst->Alpha.WriteMask ? 1 << 14 : 0;
384 | (inst->DstReg.WriteMask << 11)
|
| radeon_emulate_loops.c | 391 dst->WriteMask & (rc_swizzle_to_writemask(src->Swizzle))) {
|
| /external/mesa3d/src/mesa/state_tracker/ |
| st_tgsi_lower_yuv.c | 67 dst->Register.WriteMask &= wrmask;
68 assert(dst->Register.WriteMask);
240 ctx->tmp[i].dst.Register.WriteMask = TGSI_WRITEMASK_XYZW;
|
| st_mesa_to_tgsi.c | 251 DstReg->WriteMask );
344 if (dst.WriteMask == 0)
366 if (dst.WriteMask & bit) {
[all...] |
| /external/mesa3d/src/mesa/swrast/ |
| s_stencil.c | 134 const GLubyte wrtmask = ctx->Stencil.WriteMask[face];
502 const GLuint stencilMask = ctx->Stencil.WriteMask[0];
527 /* need to apply writemask */
556 const GLuint writeMask = ctx->Stencil.WriteMask[0];
563 if (!rb || writeMask == 0)
573 if ((writeMask & stencilMax) != stencilMax) {
592 GLubyte clear = ctx->Stencil.Clear & writeMask & 0xff;
593 GLubyte mask = (~writeMask) & 0xff;
619 GLuint clear = (ctx->Stencil.Clear & writeMask & 0xff) << 24
[all...] |
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_ureg.h | 77 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */
515 * writemask.
521 dst.WriteMask == 0;
[all...] |
| tgsi_scan.c | 805 arrays[dst->Indirect.ArrayID - 1].writemask |= dst->Register.WriteMask;
809 arrays[j].writemask |= dst->Register.WriteMask;
818 array->writemask |= dst->Register.WriteMask;
880 dst->Register.WriteMask != TGSI_WRITEMASK_XYZW)
|
| tgsi_util.c | 177 unsigned write_mask = inst->Dst[0].Register.WriteMask;
|
| tgsi_exec.h | 52 ((INST)->Dst[0].Register.WriteMask & (1 << (CHAN)))
144 unsigned writemask; member in struct:tgsi_buffer_params
|
| tgsi_build.c | 1012 dst_register.WriteMask = TGSI_WRITEMASK_XYZW;
1038 dst_register.WriteMask = mask;
1215 reg->Register.WriteMask,
[all...] |
| tgsi_sanity.c | 346 if (!inst->Dst[i].Register.WriteMask) {
347 report_error(ctx, "Destination register has empty writemask");
|
| /external/mesa3d/src/mesa/drivers/common/ |
| driverfuncs.c | 288 ctx->Driver.StencilMaskSeparate(ctx, GL_FRONT, ctx->Stencil.WriteMask[0]);
289 ctx->Driver.StencilMaskSeparate(ctx, GL_BACK, ctx->Stencil.WriteMask[1]);
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc.h | 267 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */
|
| /external/mesa3d/src/gallium/state_trackers/nine/ |
| nine_ff.c | 624 unsigned c, writemask; local
658 tmp.WriteMask = TGSI_WRITEMASK_XYZ;
668 tmp.WriteMask = TGSI_WRITEMASK_XYZW;
672 tmp.WriteMask = TGSI_WRITEMASK_XYZ;
694 tmp.WriteMask = TGSI_WRITEMASK_XYZW;
707 writemask = TGSI_WRITEMASK_XYZW;
726 writemask = (1 << dim_output) - 1;
730 ureg_MOV(ureg, ureg_writemask(oTex, writemask), ureg_src(transformed));
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| i915_state.c | 70 front_writemask = ctx->Stencil.WriteMask[0];
77 back_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
85 front_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
92 back_writemask = ctx->Stencil.WriteMask[0];
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/nouveau/ |
| nv10_state_raster.c | 162 PUSH_DATA (push, ctx->Stencil.WriteMask[0]);
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_wm.c | 478 if (ctx->Stencil.WriteMask[0] ||
479 ctx->Stencil.WriteMask[ctx->Stencil._BackFace])
|
| /external/mesa3d/src/mesa/program/ |
| prog_print.c | 490 _mesa_writemask_string(GLuint writeMask)
495 if (writeMask == WRITEMASK_XYZW)
499 if (writeMask & WRITEMASK_X)
501 if (writeMask & WRITEMASK_Y)
503 if (writeMask & WRITEMASK_Z)
505 if (writeMask & WRITEMASK_W)
522 _mesa_writemask_string(dstReg->WriteMask));
528 _mesa_writemask_string(dstReg->WriteMask));
|
| /external/mesa3d/src/gallium/include/pipe/ |
| p_shader_tokens.h | 789 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */
|
| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| etnaviv_compiler.c | 640 return (!(dst.WriteMask & TGSI_WRITEMASK_X) || src.SwizzleX == TGSI_SWIZZLE_X) &&
641 (!(dst.WriteMask & TGSI_WRITEMASK_Y) || src.SwizzleY == TGSI_SWIZZLE_Y) &&
642 (!(dst.WriteMask & TGSI_WRITEMASK_Z) || src.SwizzleZ == TGSI_SWIZZLE_Z) &&
643 (!(dst.WriteMask & TGSI_WRITEMASK_W) || src.SwizzleW == TGSI_SWIZZLE_W);
892 .comps = in->Register.WriteMask,
901 in->Register.WriteMask);
[all...] |
