| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.cc | 859 // an Adc. Adc and Rsc are equivalent using a bitwise NOT:
860 // adc rd, rn, operand <-> rsc rd, NOT(rn), operand
876 adc(cond, rd, negated_rn, operand);
[all...] |
| assembler-aarch32.h | 1848 void adc(Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
1851 void adc(Condition cond, Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
1854 void adc(EncodingSize size, function in class:vixl::aarch32::Assembler
[all...] |
| /external/zlib/src/contrib/masmx64/ |
| gvmat64.asm | 470 adc rdx, 0
|
| /external/zlib/src/contrib/masmx86/ |
| match686.asm | 386 adc edx, 0
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/score/ |
| branch_32.d | 79 adc: 93ff 0dc2 bleu 0x89e
|
| /toolchain/binutils/binutils-2.27/zlib/contrib/masmx64/ |
| gvmat64.asm | 470 adc rdx, 0
|
| /toolchain/binutils/binutils-2.27/zlib/contrib/masmx86/ |
| match686.asm | 386 adc edx, 0
|
| /art/disassembler/ |
| disassembler_x86.cc | 363 DISASSEMBLER_ENTRY(adc,
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerARM32.h | 180 void adc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
[all...] |
| /external/valgrind/none/tests/amd64/ |
| fb_test_amd64.c | 429 #define OP adc
|
| /art/runtime/interpreter/mterp/out/ |
| mterp_arm.S | [all...] |
| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| assembler_arm.h | 468 // Moved to ARM32::AssemblerARM32::adc()
469 void adc(Register rd, Register rn, Operand o, Condition cond = AL);
[all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-rn-operand-const-a32.cc | 52 M(adc) \
[all...] |
| test-assembler-cond-rd-rn-operand-const-t32.cc | 52 M(adc) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-a32.cc | 52 M(adc) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc | 52 M(adc) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 52 M(adc) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 52 M(adc) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 52 M(adc) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 52 M(adc) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-t32.cc | 52 M(adc) \
[all...] |
| /external/v8/src/compiler/arm/ |
| code-generator-arm.cc | [all...] |
| /external/v8/src/ia32/ |
| assembler-ia32.cc | 744 void Assembler::adc(Register dst, int32_t imm32) { function in class:v8::internal::Assembler
750 void Assembler::adc(Register dst, const Operand& src) { function in class:v8::internal::Assembler
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| fp_cvt_int.d | 703 adc: 9e033ce7 ucvtf s7, x7, #49
|
| /external/v8/src/arm/ |
| assembler-arm.h | 831 void adc(Register dst, Register src1, const Operand& src2,
[all...] |
