| /frameworks/ml/nn/runtime/test/specs/V1_1/ |
| relu6_float_2_relaxed.mod.py | 20 d0 = 2 variable
25 i0 = Input("input", "TENSOR_FLOAT32", "{%d, %d, %d, %d}" % (d0, d1, d2, d3))
27 output = Output("output", "TENSOR_FLOAT32", "{%d, %d, %d, %d}" % (d0, d1, d2, d3))
33 rng = d0 * d1 * d2 * d3
|
| relu_float_2_relaxed.mod.py | 20 d0 = 2 variable
25 i0 = Input("input", "TENSOR_FLOAT32", "{%d, %d, %d, %d}" % (d0, d1, d2, d3))
27 output = Output("output", "TENSOR_FLOAT32", "{%d, %d, %d, %d}" % (d0, d1, d2, d3))
33 rng = d0 * d1 * d2 * d3
|
| /platform_testing/scripts/perf-setup/ |
| angler-setup.sh | 27 echo 0 > /sys/class/kgsl/kgsl-3d0/bus_split
28 echo 1 > /sys/class/kgsl/kgsl-3d0/force_clk_on
29 echo 10000 > /sys/class/kgsl/kgsl-3d0/idle_timer
33 echo performance > /sys/class/kgsl/kgsl-3d0/devfreq/governor
34 echo 305000000 > /sys/class/kgsl/kgsl-3d0/devfreq/min_freq
35 echo 305000000 > /sys/class/kgsl/kgsl-3d0/devfreq/max_freq
37 echo 4 > /sys/class/kgsl/kgsl-3d0/min_pwrlevel
38 echo 4 > /sys/class/kgsl/kgsl-3d0/max_pwrlevel
|
| bullhead-setup.sh | 25 echo 0 > /sys/class/kgsl/kgsl-3d0/bus_split
26 echo 1 > /sys/class/kgsl/kgsl-3d0/force_clk_on
27 echo 10000 > /sys/class/kgsl/kgsl-3d0/idle_timer
31 echo performance > /sys/class/kgsl/kgsl-3d0/devfreq/governor
32 echo 300000000 > /sys/class/kgsl/kgsl-3d0/devfreq/min_freq
33 echo 300000000 > /sys/class/kgsl/kgsl-3d0/devfreq/max_freq
35 echo 4 > /sys/class/kgsl/kgsl-3d0/min_pwrlevel
36 echo 4 > /sys/class/kgsl/kgsl-3d0/max_pwrlevel
|
| b1c1-setup.sh | 53 echo 0 > /sys/class/kgsl/kgsl-3d0/bus_split
55 echo 1 > /sys/class/kgsl/kgsl-3d0/force_clk_on
57 echo 10000 > /sys/class/kgsl/kgsl-3d0/idle_timer
65 echo performance > /sys/class/kgsl/kgsl-3d0/devfreq/governor
67 cat /sys/class/kgsl/kgsl-3d0/devfreq/cur_freq
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| armv8-a+fp.s | 11 vseleq.f64 d0, d0, d0
19 vmaxnm.f64 d0, d0, d0
27 vminnm.f64 d0, d0, d0
35 vcvta.s32.f64 s0, d0
[all...] |
| macro-vld1.s | 9 sfi_breg r0, vld1.8 {d0}, [\B]
10 sfi_breg r0, vld1.8 { d0 }, [\B]
|
| vfp-bad.l | 2 [^:]*:4: Error: instruction does not support writeback -- `fstd d0,\[r0\],#8'
3 [^:]*:5: Error: instruction does not support writeback -- `fstd d0,\[r0,#-8\]!'
6 [^:]*:8: Error: instruction does not support writeback -- `fldd d0,\[r0\],#8'
7 [^:]*:9: Error: instruction does not support writeback -- `fldd d0,\[r0,#-8\]!'
|
| vfp-bad_t2.l | 2 [^:]*:7: Error: instruction does not support writeback -- `fstd d0,\[r0\],#8'
3 [^:]*:8: Error: instruction does not support writeback -- `fstd d0,\[r0,#-8\]!'
6 [^:]*:11: Error: instruction does not support writeback -- `fldd d0,\[r0\],#8'
7 [^:]*:12: Error: instruction does not support writeback -- `fldd d0,\[r0,#-8\]!'
|
| vfp-fma-arm.d | 9 0[0-9a-f]+ <[^>]+> eea10b02 vfma\.f64 d0, d1, d2
11 0[0-9a-f]+ <[^>]+> 0ea10b02 vfmaeq\.f64 d0, d1, d2
13 0[0-9a-f]+ <[^>]+> eea10b42 vfms\.f64 d0, d1, d2
15 0[0-9a-f]+ <[^>]+> 0ea10b42 vfmseq\.f64 d0, d1, d2
17 0[0-9a-f]+ <[^>]+> ee910b42 vfnma\.f64 d0, d1, d2
19 0[0-9a-f]+ <[^>]+> 0e910b42 vfnmaeq\.f64 d0, d1, d2
21 0[0-9a-f]+ <[^>]+> ee910b02 vfnms\.f64 d0, d1, d2
23 0[0-9a-f]+ <[^>]+> 0e910b02 vfnmseq\.f64 d0, d1, d2
|
| armv8-a+simd.s | 6 vmaxnm.f32 d0, d0, d0
14 vminnm.f32 d0, d0, d0
22 vcvta.s32.f32 d0, d0
30 vrinta.f32 d0, d0
[all...] |
| armv7e-m+fpv5-d16.s | 11 vseleq.f64 d0, d0, d0
19 vmaxnm.f64 d0, d0, d0
27 vminnm.f64 d0, d0, d0
35 vcvta.s32.f64 s0, d0
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/m68k/ |
| mode5.d | 13 6: 4cd6 00ff moveml %fp@,%d0-%d7
14 a: 48d6 00ff moveml %d0-%d7,%fp@
|
| mode5.s | 7 movem.l 0(%a6),%d0-%d7
8 movem.l %d0-%d7,0(%a6)
|
| movem-offset.s | 6 movem.l -24(%a6),%d0-%d7/%a0-%a1
7 movem.l %d0-%d7/%a0-%a1,16(%a6)
|
| p13050-1.s | 2 move.b (2,%a0,%d0.l),1(%a1)
|
| cpu32.d | 11 [ 0-9a-f]+: f800 2001 tblub %d0,%d1,%d2
12 [ 0-9a-f]+: f800 2041 tbluw %d0,%d1,%d2
13 [ 0-9a-f]+: f800 2081 tblul %d0,%d1,%d2
14 [ 0-9a-f]+: f800 2401 tblunb %d0,%d1,%d2
15 [ 0-9a-f]+: f800 2441 tblunw %d0,%d1,%d2
16 [ 0-9a-f]+: f800 2481 tblunl %d0,%d1,%d2
17 [ 0-9a-f]+: f800 2801 tblsb %d0,%d1,%d2
18 [ 0-9a-f]+: f800 2841 tblsw %d0,%d1,%d2
19 [ 0-9a-f]+: f800 2881 tblsl %d0,%d1,%d2
20 [ 0-9a-f]+: f800 2c01 tblsnb %d0,%d1,%d
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mri/ |
| for.d | 11 0+002 <foo\+(0x|)2> movew #1,%d0
12 0+006 <foo\+(0x|)6> cmpiw #10,%d0
14 0+00c <foo\+(0x|)c> addw %d0,%d1
17 0+012 <foo\+(0x|)12> addqw #2,%d0
20 0+018 <foo\+(0x|)18> movew #10,%d0
21 0+01c <foo\+(0x|)1c> cmpiw #1,%d0
26 0+02a <foo\+(0x|)2a> addw %d0,%d1
27 0+02c <foo\+(0x|)2c> subqw #1,%d0
|
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-mn10300/ |
| i112045-3.d | 15 109:[ ]+00[ ]+clr[ ]+d0
16 10a:[ ]+03 00 00[ ]+movhu[ ]+d0,\(0 <L001-0x100>\)
|
| i127740.d | 14 200: 00[ ]+clr d0
15 201: 02 00 00[ ]+movbu d0,\(0 <_main-0x100>\)
|
| i112045-1.d | 7 0: fc d0 f8 0f[ ]+add 4088,a0
13 8: fc d0 2b 01[ ]+add 299,a0
19 10: fc d0 08 00[ ]+add 8,a0
|
| /external/capstone/suite/MC/AArch64/ |
| neon-scalar-add-sub.s.cs | 2 0x1f,0x84,0xf0,0x5e = add d31, d0, d16
|
| /external/libmpeg2/common/arm/ |
| ideint_cac_a9.s | 150 vadd.u32 d21, d0, d1
160 vabd.u8 d0, d0, d1
166 vcge.u8 d1, d0, d9
167 vand.u8 d0, d0, d1
168 @ d0 now contains 8 absolute diff of sums above the threshold
171 vpaddl.u8 d0, d0
172 vshl.u16 d0, d0, #
[all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-scalar-reduce-pairwise.s | 6 addp d0, v1.2d
8 // CHECK: addp d0, v1.2d // encoding: [0x20,0xb8,0xf1,0x5e]
|
| /art/runtime/interpreter/mterp/arm/ |
| funopWider.S | 3 * "instr" line that specifies an instruction that performs "d0 = op s0".
13 $instr @ d0<- op
17 fstd d0, [r9] @ vA<- d0
|
