| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips5-wrong-error.s | 9 abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
20 c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 14 ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips5-wrong-error.s | 9 abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
20 c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips5-wrong-error.s | 8 abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
23 c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /prebuilts/go/darwin-x86/test/ |
| escape5.go | 132 func f8(p *T1) (k T2) { // ERROR "leaking param: p to result k" "leaking param: p" func
145 f8(&j) // ERROR "&j escapes to heap"
|
| /prebuilts/go/linux-x86/test/ |
| escape5.go | 132 func f8(p *T1) (k T2) { // ERROR "leaking param: p to result k" "leaking param: p" func
145 f8(&j) // ERROR "&j escapes to heap"
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/crx/ |
| cmpbr_insn.d | 78 ac: cc 30 f8 2c cmpbltb \$0xc, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
87 c4: cd 31 f8 9d cmpbgeb \$0x30, r9, 0x[0-9a-f]* [-_<>+0-9a-z]*
109 f8: 9f 31 00 e4 cmpbhiw r15, r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
159 176: dc 30 f8 2c cmpbltw \$0xc, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
168 18e: dd 31 f8 9d cmpbgew \$0x30, r9, 0x[0-9a-f]* [-_<>+0-9a-z]*
210 1f8: f9 ff
240 240: ec 30 f8 2c cmpbltd \$0xc, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
249 258: ed 31 f8 9d cmpbged \$0x30, r9, 0x[0-9a-f]* [-_<>+0-9a-z]*
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/d30v/ |
| reloc.d | 62 f8: 80180000 80000000 jmp.l 0 <start>
63 f8: R_D30V_32 unknown
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/i386/ |
| avx512ifma_vl-intel.d | 24 [ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 b2 f8 fb ff ff[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]\{1to2\}
37 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 f8 fb ff ff[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x408\]\{1to4\}
50 [ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 b2 f8 fb ff ff[ ]*vpmadd52huq xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]\{1to2\}
63 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 f8 fb ff ff[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x408\]\{1to4\}
76 [ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 b2 f8 fb ff ff[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]\{1to2\}
89 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 f8 fb ff ff[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x408\]\{1to4\}
102 [ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 b2 f8 fb ff ff[ ]*vpmadd52huq xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]\{1to2\}
115 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 f8 fb ff ff[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x408\]\{1to4\}
|
| avx512ifma_vl.d | 24 [ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
37 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
50 [ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
63 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
76 [ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
89 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
102 [ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
115 [ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
| rexw.d | 22 [ ]*[a-f0-9]+: c5 f8 50 ca vmovmskps %xmm2,%ecx
41 [ ]*[a-f0-9]+: c5 f8 50 ca vmovmskps %xmm2,%ecx
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/i386/ilp32/ |
| rexw.d | 23 [ ]*[a-f0-9]+: c5 f8 50 ca vmovmskps %xmm2,%ecx
42 [ ]*[a-f0-9]+: c5 f8 50 ca vmovmskps %xmm2,%ecx
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| micromips@24k-triple-stores-1.d | 70 *[0-9a-f]+: 55a8 4108 sdxc1 \$f8,t5\(t0\)
75 *[0-9a-f]+: 55a8 4188 suxc1 \$f8,t5\(t0\)
|
| mips4-fp.s | 13 madd.s $f10,$f8,$f2,$f0
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mmix/ |
| regt-op-r.d | 71 f8: af3b0c00 stou \$59,\$12,0
135 1f8: 9f172600 go \$23,\$38,0
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/ppc/ |
| e500.d | 48 98: (10 a0 22 f8|f8 22 a0 10) efdctuiz r5,r4
|
| 476.d | 65 dc: (7c 83 2b f8|f8 2b 83 7c) cmpb r3,r4,r5
66 e0: (7c 83 2b f8|f8 2b 83 7c) cmpb r3,r4,r5
72 f8: (2b 83 00 a7|a7 00 83 2b) cmplwi cr7,r3,167
136 1f8: (fd 40 5e 5c|5c 5e 40 fd) fctid f10,f11
187 2c4: (fd 00 48 19|19 48 00 fd) frsp\. f8,f9
200 2f8: (ed 4b 60 28|28 60 4b ed) fsubs f10,f11,f12
235 384: (7e f8 ca 2e|2e ca f8 7e) lhzx r23,r24,r2
[all...] |
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-arm/ |
| tls-descrelax-be32.d | 30 8054: 000080f8 .word 0x000080f8
88 80f8: 4802 ldr r0, \[pc, #8\] ; \(8104 <bar\+0x64>\)
|
| tls-descrelax-be8.d | 30 8054: 000080f8 .word 0x000080f8
88 80f8: 4802 ldr r0, \[pc, #8\] ; \(8104 <bar\+0x64>\)
|
| tls-descrelax-v7.d | 30 8054: 000080f8 .word 0x000080f8
88 80f8: 4802 ldr r0, \[pc, #8\] ; \(8104 <bar\+0x64>\)
|
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-frv/ |
| tls-relax-shared-1.d | 44 [0-9a-f ]+: 90 fc f8 20 setlos 0xf*fffff820,gr8
46 [0-9a-f ]+: 92 fc f8 10 setlos 0xf*fffff810,gr9
|
| tls-shared-1.d | 44 [0-9a-f ]+: 90 fc f8 20 setlos 0xf*fffff820,gr8
46 [0-9a-f ]+: 92 fc f8 10 setlos 0xf*fffff810,gr9
|
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-mips-elf/ |
| eh-frame3.d | 147 0+01f8 0+0014 0+01fc FDE cie=0+0000 pc=0+0201f0..0+020210
202 0+02f8 0+001c 0+01b4 FDE cie=0+0148 pc=0+020340..0+020370
|
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-powerpc/ |
| tlsexe.d | 21 .* (f8 41 00 28|28 00 41 f8) std r2,40\(r1\)
|
| tlsso.d | 12 .* (f8 41 00 28|28 00 41 f8) std r2,40\(r1\)
|
