| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/sh/sh64/ |
| basic-1.s | 96 fsub.d dr0,dr44,dr32
97 fsub.s fr3,fr62,fr3
|
| basic-1.d | 98 [ ]+164:[ ]+3403b200[ ]+fsub\.d dr0,dr44,dr32
99 [ ]+168:[ ]+3432f830[ ]+fsub\.s fr3,fr62,fr3
|
| /external/llvm/test/MC/X86/ |
| x86-16.s | 227 // CHECK: fsub %st(0)
229 fsub %st(0), %st
|
| x86-32.s | 333 // CHECK: fsub %st(0)
335 fsub %st(0), %st
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/ia64/ |
| opc-f.d | 296 5f6: 40 30 14 02 50 00 fsub\.s0 f4=f5,f6
299 606: 40 30 14 02 50 00 fsub\.s0 f4=f5,f6
302 616: 40 30 14 02 51 00 fsub\.s1 f4=f5,f6
305 626: 40 30 14 02 52 00 fsub\.s2 f4=f5,f6
308 636: 40 30 14 02 53 00 fsub\.s3 f4=f5,f6
311 646: 40 30 14 02 54 00 fsub\.s\.s0 f4=f5,f6
314 656: 40 30 14 02 54 00 fsub\.s\.s0 f4=f5,f6
317 666: 40 30 14 02 55 00 fsub\.s\.s1 f4=f5,f6
320 676: 40 30 14 02 56 00 fsub\.s\.s2 f4=f5,f6
323 686: 40 30 14 02 57 00 fsub\.s\.s3 f4=f5,f
[all...] |
| /external/llvm/test/MC/AArch64/ |
| arm64-fp-encoding.s | 156 fsub h1, h2, h3
157 fsub s1, s2, s3
158 fsub d1, d2, d3
160 ; FP16: fsub h1, h2, h3 ; encoding: [0x41,0x38,0xe3,0x1e]
162 ; NO-FP16-NEXT: fsub h1, h2, h3
163 ; CHECK: fsub s1, s2, s3 ; encoding: [0x41,0x38,0x23,0x1e]
164 ; CHECK: fsub d1, d2, d3 ; encoding: [0x41,0x38,0x63,0x1e]
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| advsimd-fp16.d | 65 [0-9a-f]+: 4ee3d441 fsub v1.2d, v2.2d, v3.2d
66 [0-9a-f]+: 0ea3d441 fsub v1.2s, v2.2s, v3.2s
67 [0-9a-f]+: 4ea3d441 fsub v1.4s, v2.4s, v3.4s
68 [0-9a-f]+: 0ec01400 fsub v0.4h, v0.4h, v0.4h
69 [0-9a-f]+: 0ec31441 fsub v1.4h, v2.4h, v3.4h
70 [0-9a-f]+: 4ec01400 fsub v0.8h, v0.8h, v0.8h
71 [0-9a-f]+: 4ec31441 fsub v1.8h, v2.8h, v3.8h
|
| /toolchain/binutils/binutils-2.27/opcodes/ |
| rx-decode.opc | 901 /** 1111 1101 0111 0010 0000 rdst fsub #%1, %0 */
902 ID(fsub); DR(rdst); SC(IMM(0)); F__SZ_;
904 /** 1111 1100 1000 00sd rsrc rdst fsub %1%S1, %0 */
905 ID(fsub); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
1099 /** 1111 1111 1000 rdst srca srcb fsub %2, %1, %0 */
1100 ID(fsub); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
|
| /external/swiftshader/third_party/LLVM/test/MC/X86/ |
| x86-32.s | 305 // CHECK: fsub %st(0)
307 fsub %st(0), %st
|
| /external/valgrind/auxprogs/ |
| ppcfround.c | 254 INSN(fsub, "fsub %%f4, %%f1,%%f2");
255 INSN(fsub_, "fsub. %%f4, %%f1,%%f2");
469 do_N_binary("fsub", insn_fsub, args, nargs, SHOW_ALL);
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mmix/ |
| list-in-n.d | 28 4c: 0670df29 fsub \$112,\$223,\$41
|
| list-in-r.d | 28 4c: 0670df29 fsub \$112,\$223,\$41
|
| list-in-rn.d | 28 4c: 0670df29 fsub \$112,\$223,\$41
|
| list-insns.d | 26 4c: 0670df29 fsub \$112,\$223,\$41
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/pdp11/ |
| opcode.d | 80 9c: 7a09 [ ]*fsub r1
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/pj/ |
| ops.d | 174 8c: 66 fsub
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/visium/ |
| allinsn_gr5.d | 144 208: 93 e0 8c 9c fsub f3,f0,f9
|
| allinsn_gr6.d | 144 208: 93 e0 8c 9c fsub f3,f0,f9
|
| /bionic/libm/x86/ |
| libm_reduce_pi04l.S | 103 fsub %st(2), %st
132 fsub %st(2), %st
229 fsub %st, %st(3)
293 fsub %st(3), %st
[all...] |
| /external/llvm/test/Bindings/OCaml/ |
| core.ml | 259 * CHECK: @const_fneg = global double fsub
268 * CHECK: @const_fsub = global double fsub
[all...] |
| /external/swiftshader/third_party/LLVM/test/Bindings/Ocaml/ |
| vmcore.ml | 208 * RUN: grep {@const_fneg = global double fsub } < %t.ll
217 * RUN: grep {@const_fsub = global double fsub } < %t.ll
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/sh/arch/ |
| sh2a-or-sh4.s | 39 fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
229 fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
|
| sh4.s | [all...] |
| sh4a.s | [all...] |
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-sh/arch/ |
| sh2a-or-sh4.s | 39 fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
229 fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
|
