| /external/tensorflow/tensorflow/contrib/lite/models/smartreply/ops/ |
| extract_feature.cc | 89 label->data.i32[i] = 0;
90 weight->data.i32[i] = 0;
96 label->data.i32[i] = static_cast<int32_t>(feature_id);
102 label->data.i32[0] = 0;
103 weight->data.i32[0] = 0;
|
| /prebuilts/go/darwin-x86/test/ |
| bounds.go | 29 i32 int32
87 use(s[i32])
88 use(a1[i32])
89 use(a1k[i32])
90 use(a100k[i32])
91 use(p1[i32])
92 use(p1k[i32])
93 use(p100k[i32])
206 use(s[i32>>22])
207 use(a1[i32>>22]
28 i32 int32 var
[all...] |
| /prebuilts/go/linux-x86/test/ |
| bounds.go | 29 i32 int32
87 use(s[i32])
88 use(a1[i32])
89 use(a1k[i32])
90 use(a100k[i32])
91 use(p1[i32])
92 use(p1k[i32])
93 use(p100k[i32])
206 use(s[i32>>22])
207 use(a1[i32>>22]
28 i32 int32 var
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | 50 Cond.getOperand(0).getValueType() == MVT::i32 && Cond.hasOneUse();
230 CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
294 assert(EltVT.bitsEq(MVT::i32));
315 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
330 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
342 MVT::i32);
354 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32);
370 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32);
371 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
372 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
[all...] |
| /external/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| LowLevel.cpp | 277 TestRegReg(cmp, eax, ecx, i32, 2, 0x3B, 0xC1);
278 TestRegReg(cmp, ecx, edx, i32, 2, 0x3B, 0xCA);
279 TestRegReg(cmp, edx, ebx, i32, 2, 0x3B, 0xD3);
280 TestRegReg(cmp, ebx, esp, i32, 2, 0x3B, 0xDC);
281 TestRegReg(cmp, esp, ebp, i32, 2, 0x3B, 0xE5);
282 TestRegReg(cmp, ebp, esi, i32, 2, 0x3B, 0xEE);
283 TestRegReg(cmp, esi, edi, i32, 2, 0x3B, 0xF7);
284 TestRegReg(cmp, edi, r8, i32, 3, 0x41, 0x3B, 0xF8);
285 TestRegReg(cmp, r8, r9, i32, 3, 0x45, 0x3B, 0xC1);
286 TestRegReg(cmp, r9, r10, i32, 3, 0x45, 0x3B, 0xCA)
[all...] |
| /external/mesa3d/src/amd/common/ |
| ac_nir_to_llvm.c | 95 LLVMTypeRef i32; member in struct:nir_to_llvm_context
267 offset = LLVMConstInt(ctx->i32, idx * 16, false);
280 return LLVMBuildBitCast(ctx->builder, v, ctx->i32, "");
284 LLVMTypeRef nt = LLVMVectorType(ctx->i32, LLVMGetVectorSize(type));
294 if (type == ctx->i32) {
298 if (elem_type == ctx->i32) {
313 LLVMConstInt(ctx->i32, rshift, false), "");
318 LLVMConstInt(ctx->i32, mask, false), "");
412 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
414 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsISelLowering.cpp | 89 // Mips does not have i1 type, so use i32 for
95 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
122 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
125 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
127 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
128 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
129 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
130 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
133 setOperationAction(ISD::SELECT, MVT::i32, Custom);
135 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom)
[all...] |
| /external/llvm/test/MC/ARM/ |
| neont2-bitwise-encoding.s | 20 @ vorr.i32 d16, #0x1000000
21 @ vorr.i32 q8, #0x1000000
22 @ vorr.i32 q8, #0x0
30 @ vbic.i32 d16, #0xFF000000
31 @ vbic.i32 q8, #0xFF000000
|
| neon-mul-encoding.s | 5 vmul.i32 d16, d16, d17
9 vmul.i32 q8, q8, q9
17 vmul.i32 d16, d17
21 vmul.i32 q8, q9
28 @ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0xb1,0x09,0x60,0xf2]
32 @ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0xf2,0x09,0x60,0xf2]
40 @ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0xb1,0x09,0x60,0xf2]
44 @ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0xf2,0x09,0x60,0xf2]
109 vmul.i32 d3, d2[0]
117 vmul.i32 q3, d2[0
[all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| neont2-bitwise-encoding.s | 20 @ vorr.i32 d16, #0x1000000
21 @ vorr.i32 q8, #0x1000000
22 @ vorr.i32 q8, #0x0
30 @ vbic.i32 d16, #0xFF000000
31 @ vbic.i32 q8, #0xFF000000
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 50 addRegisterClass(MVT::i32, BF::DRegisterClass);
60 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
61 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
80 setOperationAction(ISD::SDIV, MVT::i32, Expand);
82 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
84 setOperationAction(ISD::SREM, MVT::i32, Expand);
86 setOperationAction(ISD::UDIV, MVT::i32, Expand);
88 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
90 setOperationAction(ISD::UREM, MVT::i32, Expand);
92 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand)
[all...] |
| /external/llvm/test/Bindings/OCaml/ |
| core.ml | 73 insist ("i32" = (string_of_lltype i32_type));
75 insist ("i32 42" = (string_of_llvalue c))
100 (* CHECK: const_int{{.*}}i32{{.*}}-1
125 (* CHECK: const_int_string{{.*}}i32{{.*}}-1
202 (* CHECK: const_array{{.*}}[i32 3, i32 4]
219 (* CHECK: const_structure{{.*.}}i16 1, i16 2, i32 3, i32 4
364 * CHECK: const_shufflevector = global <4 x i32> <i32 0, i32 1, i32 1, i32 0
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 81 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
101 MVT::i32);
117 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
244 SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32,
246 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32,
263 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
265 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
272 MVT::i32),
274 CurDAG->getTargetConstant(SP::sub_even, dl, MVT::i32),
276 CurDAG->getTargetConstant(SP::sub_odd, dl, MVT::i32),
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 118 return CurDAG->getTargetConstant(bitPos, DL, MVT::i32);
140 // type i32 where the negative literal is transformed into a positive literal
144 return CurDAG->getTargetConstant(-Imm, DL, MVT::i32);
156 return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
162 return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
167 return CurDAG->getTargetConstant(Imm - 2, DL, MVT::i32);
172 return CurDAG->getTargetConstant(Imm - 3, DL, MVT::i32);
268 case MVT::i32:
300 SDValue IncV = CurDAG->getTargetConstant(Inc, dl, MVT::i32);
307 SDValue Zero = CurDAG->getTargetConstant(0, dl, MVT::i32);
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| simd_by_scalar_low_regbank.s | 2 .irp op, vmul.i16 vmul.f16 vmul.i32 vmul.f32
9 .irp op, vmla.i16 vmla.i32 vmla.f16 vmla.f32 vmls.i16 vmls.i32 vmls.f16 vmls.f32
|
| simd_by_scalar_low_regbank.l | 2 [^:]*:21: Error: scalar out of range for multiply instruction -- `vmul.i32 d3,d12,d7\[2\]'
3 [^:]*:21: Error: scalar out of range for multiply instruction -- `vmul.i32 q3,q12,d7\[2\]'
14 [^:]*:23: Error: scalar out of range for multiply instruction -- `vmul.i32 d13,d6,d15\[3\]'
15 [^:]*:23: Error: scalar out of range for multiply instruction -- `vmul.i32 q13,q6,d15\[3\]'
18 [^:]*:25: Error: scalar out of range for multiply instruction -- `vmla.i32 d5,d4,d6\[2\]'
19 [^:]*:25: Error: scalar out of range for multiply instruction -- `vmla.i32 q5,q4,d6\[2\]'
22 [^:]*:25: Error: scalar out of range for multiply instruction -- `vmls.i32 d5,d4,d6\[2\]'
23 [^:]*:25: Error: scalar out of range for multiply instruction -- `vmls.i32 q5,q4,d6\[2\]'
36 [^:]*:27: Error: scalar out of range for multiply instruction -- `vmla.i32 d12,d6,d13\[3\]'
37 [^:]*:27: Error: scalar out of range for multiply instruction -- `vmla.i32 q12,q6,d13\[3\]
[all...] |
| neon-cov.d | 281 0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5
282 0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5
283 0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 ; 0x000000a5
284 0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500
285 0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500
286 0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 ; 0x0000a500
287 0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000
288 0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000
289 0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 ; 0x00a50000
290 0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa500000
[all...] |
| /external/clang/test/Sema/ |
| format-strings-ms.c | 11 void non_iso_warning_test(__int32 i32, __int64 i64, wchar_t c, void *p) {
12 printf("%Id", i32); // expected-warning{{'I' length modifier is not supported by ISO C}}
13 printf("%I32d", i32); // expected-warning{{'I32' length modifier is not supported by ISO C}}
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.cpp | 90 // Extend or truncate the argument to be an i32 value for the call.
91 if (Src.getValueType().bitsGT(MVT::i32))
92 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
93 else if (Src.getValueType().bitsLT(MVT::i32))
94 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
152 EVT VT = MVT::i32;
178 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other, MVT::Glue);
187 DAG.getConstant(NumRegs, dl, MVT::i32));
213 DAG.getNode(ISD::ADD, dl, MVT::i32, Src
[all...] |
| /device/linaro/bootloader/edk2/AppPkg/Applications/Sockets/SetSockOpt/ |
| SetSockOpt.c | 87 INT32 * i32;
member in union:__anon4893
118 Print ( L"%d", *Value.i32 );
128 if (( SOCK_STREAM <= *Value.i32 ) && ( SOCK_SEQPACKET >= *Value.i32 )) {
129 pString = mSocketType[ *Value.i32 - SOCK_STREAM ];
133 Print ( L"%08x (unknown type)", *Value.i32 );
178 INT32 * i32;
member in union:__anon4894
199 Values = sscanf ( pValue, "%d", Value.i32 );
201 BytesToWrite = sizeof ( *Value.i32);
|
| /external/capstone/suite/MC/ARM/ |
| neon-bitcount-encoding.s.cs | 6 0xa0,0x04,0xf8,0xf3 = vclz.i32 d16, d16
9 0xe0,0x04,0xf8,0xf3 = vclz.i32 q8, q8
|
| neont2-bitcount-encoding.s.cs | 6 0xf8,0xff,0xa0,0x04 = vclz.i32 d16, d16
9 0xf8,0xff,0xe0,0x04 = vclz.i32 q8, q8
|
| /external/icu/icu4c/source/common/ |
| resource.h | 50 ResourceArray(const uint16_t *i16, const uint32_t *i32, int32_t len) :
51 items16(i16), items32(i32), length(len) {}
83 const uint16_t *i16, const uint32_t *i32, int32_t len) :
84 keys16(k16), keys32(k32), items16(i16), items32(i32), length(len) {}
|
| /external/mesa3d/src/compiler/nir/ |
| nir_search_helpers.h | 51 if (val->i32[swizzle[i]] < 0)
53 if (!__is_power_of_two(val->i32[swizzle[i]]))
81 if (val->i32[swizzle[i]] > 0)
83 if (!__is_power_of_two(abs(val->i32[swizzle[i]])))
|
| /external/swiftshader/third_party/LLVM/test/Bindings/Ocaml/ |
| vmcore.ml | 87 (* RUN: grep {const_int.*i32.*-1} < %t.ll
109 (* RUN: grep {const_int_string.*i32.*-1} < %t.ll
153 (* RUN: grep {const_array.*\\\[i32 3, i32 4\\\]} < %t.ll
168 (* RUN: grep {const_structure.*.i16 1, i16 2, i32 3, i32 4} < %t.ll
310 * RUN: grep {const_shufflevector = global <4 x i32> <i32 0, i32 1, i32 1, i32 0>} < %t.l
[all...] |
