| /dalvik/libdex/ |
| InstrUtils.cpp | 473 #define FETCH(_offset) (insns[(_offset)])
474 #define FETCH_u4(_offset) (fetch_u4_impl((_offset), insns))
480 static inline u4 fetch_u4_impl(u4 offset, const u2* insns) {
481 return insns[offset] | ((u4) insns[offset+1] << 16);
485 * Decode the instruction pointed to by "insns".
490 void dexDecodeInstruction(const u2* insns, DecodedInstruction* pDec)
492 u2 inst = *insns;
683 size_t dexGetWidthFromInstruction(const u2* insns)
687 if (*insns == kPackedSwitchSignature)
[all...] |
| InstrUtils.h | 159 size_t dexGetWidthFromInstruction(const u2* insns);
197 * Decode the instruction pointed to by "insns".
199 void dexDecodeInstruction(const u2* insns, DecodedInstruction* pDec);
|
| /dalvik/dx/src/com/android/dx/ssa/ |
| LocalVariableExtractor.java | 106 List<SsaInsn> insns = block.getInsns(); local
107 int insnSz = insns.size();
109 // The exit block has no insns and no successors
121 SsaInsn lastInsn = insns.get(insnSz - 1);
141 SsaInsn insn = insns.get(i);
|
| /dalvik/dx/src/com/android/dx/ssa/back/ |
| RegisterAllocator.java | 136 ArrayList<SsaInsn> insns = block.getInsns(); local
137 int insnIndex = insns.indexOf(insn);
144 if (insnIndex != insns.size() - 1) {
167 insns.add(insnIndex, toAdd);
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/xgate/ |
| insns.s | 1 # Test for correct generation of XGATE insns.
|
| /toolchain/binutils/binutils-2.27/opcodes/ |
| cgen-dis.c | 64 /* Add insns sorted by the number of decodable bits, in decreasing order.
87 /* Subroutine of build_dis_hash_table to add INSNS to the hash table.
89 COUNT is the number of elements in INSNS.
101 const CGEN_INSN * insns,
115 const CGEN_INSN *insn = &insns[i];
135 /* Subroutine of build_dis_hash_table to add INSNS to the hash table.
136 This function is identical to hash_insn_array except the insns are
141 const CGEN_INSN_LIST *insns,
148 for (ilist = insns; ilist != NULL; ilist = ilist->next, ++ hentbuf)
194 /* Add compiled in insns
[all...] |
| ip2k-desc.c | 928 ??? This could leave out insns not supported by the specified mach/isa,
930 "unknown insn", so for now we include all insns and require the app to
932 ??? On the other hand, parsing of such insns may require their hardware or
940 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); local
942 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
944 insns[i].base = &ib[i];
945 cd->insn_table.init_entries = insns;
1145 const CGEN_INSN *insns; local
[all...] |
| lm32-desc.c | 915 ??? This could leave out insns not supported by the specified mach/isa,
917 "unknown insn", so for now we include all insns and require the app to
919 ??? On the other hand, parsing of such insns may require their hardware or
927 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); local
929 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
931 insns[i].base = &ib[i];
932 cd->insn_table.init_entries = insns;
1132 const CGEN_INSN *insns; local
[all...] |
| ip2k-opc.c | 663 /* Formats for ALIAS macro-insns. */
866 CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
871 memset (insns, 0, num_macros * sizeof (CGEN_INSN));
874 insns[i].base = &ib[i];
875 insns[i].opcode = &oc[i];
876 ip2k_cgen_build_insn_regex (& insns[i]);
878 cd->macro_insn_table.init_entries = insns;
883 insns = (CGEN_INSN *) cd->insn_table.init_entries;
886 insns[i].opcode = &oc[i];
887 ip2k_cgen_build_insn_regex (& insns[i])
865 CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); local
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/cris/ |
| unimplemented.s | 1 ; Test the unimplemented insns (of which some are used in xsim
3 ; You may need to remove some from here as new insns emerge.
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/i386/ |
| clflushopt-intel.d | 3 #name: i386 CLFLUSHOPT insns (Intel disassembly)
|
| clwb-intel.d | 3 #name: i386 CLWB insns (Intel disassembly)
|
| long-1-intel.d | 2 #name: i386 long insns (Intel disassembly)
|
| long-1.d | 2 #name: i386 long insns
|
| prefetchwt1-intel.d | 3 #name: i386 PREFETCHWT1 insns (Intel disassembly)
|
| rtm-intel.d | 2 #name: i386 RTM insns (Intel disassembly)
|
| rtm.d | 2 #name: i386 RTM insns
|
| x86-64-long-1.d | 2 #name: x86-64 long insns
|
| x86-64-rtm.d | 2 #name: x86-64 RTM insns
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/sparc/ |
| natural-32.d | 3 #name: sparc natural regs and insns
|
| natural.d | 3 #name: sparc natural regs and insns
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/tic6x/ |
| insns-parallel-multi.d | 4 #source: insns-parallel-multi.s
|
| /external/capstone/arch/XCore/ |
| XCoreMapping.c | 74 static insn_map insns[] = { variable
1374 i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
1376 insn->id = insns[i].mapid;
1380 memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
1381 insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
1383 memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
1384 insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod)
[all...] |
| /art/libdexfile/dex/ |
| dex_instruction.cc | 92 const uint16_t* insns = reinterpret_cast<const uint16_t*>(this); local
93 uint16_t insn = *insns;
99 const uint16_t* insns = reinterpret_cast<const uint16_t*>(this); local
101 switch (*insns) {
103 return (4 + insns[1] * 2);
105 return (2 + insns[1] * 4);
107 uint16_t element_size = insns[1];
108 uint32_t length = insns[2] | (((uint32_t)insns[3]) << 16);
113 if ((*insns & 0xFF) == 0)
123 const uint16_t* insns = reinterpret_cast<const uint16_t*>(this); local
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| BasicBlockList.java | 134 InsnList insns = one.getInsns(); local
135 int insnsSz = insns.size();
138 Insn insn = insns.get(j);
179 InsnList insns = one.getInsns(); local
180 insns.forEach(visitor);
|
