| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/sh/arch/ |
| sh3-dsp.s | 52 ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
53 ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
54 ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
55 ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,RE (…)
[all...] |
| sh-dsp.s | 14 ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
15 ldc r4,RE ;!/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
16 ldc r4,RS ;!/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
17 ldc.l @r4+,MOD ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4, (…)
[all...] |
| sh.s | 45 ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
46 ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
47 ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
48 ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,R (…)
[all...] |
| sh2.s | 58 ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
59 ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
60 ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
61 ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,R (…)
[all...] |
| sh2a-nofpu-or-sh3-nommu.s | 54 ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
55 ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
56 ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
57 ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,R (…)
[all...] |
| sh2a-nofpu-or-sh4-nommu-nofpu.s | 51 ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
52 ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
53 ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
54 ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,R (…)
[all...] |
| sh2a-or-sh3e.s | 52 ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
53 ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
54 ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
55 ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,R (…)
[all...] |
| sh2e.s | 87 ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
88 ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
89 ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
90 ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,R (…)
[all...] |
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-sh/arch/ |
| sh3-dsp.s | 52 ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
53 ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
54 ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
55 ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,RE (…)
[all...] |
| sh-dsp.s | 14 ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
15 ldc r4,RE ;!/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
16 ldc r4,RS ;!/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
17 ldc.l @r4+,MOD ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4, (…)
[all...] |
| sh.s | 45 ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
46 ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
47 ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
48 ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,R (…)
[all...] |
| sh2.s | 58 ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
59 ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
60 ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
61 ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,R (…)
[all...] |
| sh2a-nofpu-or-sh3-nommu.s | 54 ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
55 ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
56 ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
57 ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,R (…)
[all...] |
| sh2a-nofpu-or-sh4-nommu-nofpu.s | 51 ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
52 ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
53 ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
54 ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,R (…)
[all...] |
| /external/tensorflow/tensorflow/contrib/rnn/kernels/ |
| blas_gemm.h | 32 int ldb, T beta, T* c, int ldc);
|
| /external/tensorflow/tensorflow/core/kernels/ |
| cuda_solvers.cc | 331 const Scalar* B, int ldb, Scalar* C, int ldc) {
339 reinterpret_cast<CudaScalar*>(C), ldc));
350 const Scalar* B, int ldb, Scalar* C, int ldc) const { \
352 transb, m, n, alpha, A, lda, beta, B, ldb, C, ldc); \
491 int ldc, int* dev_lapack_info) {
497 CUDAComplex(dev_tau), CUDAComplex(dev_c), ldc, &lwork));
504 CUDAComplex(dev_tau), CUDAComplex(dev_c), ldc,
516 const Scalar* dev_tau, Scalar* dev_c, int ldc, \
521 dev_a, lda, dev_tau, dev_c, ldc, dev_lapack_info); \
[all...] |
| quantized_conv_ops.cc | 384 const int ldc = filter_count; local
393 -input_offset, -filter_offset, lda, ldb, ldc);
423 output_data_as_int32, m, n, ldc);
442 chunk_output_data, output_shift, output_offset, output_mult, ldc);
|
| cuda_solvers.h | 203 int ldc) const TF_MUST_USE_RESULT;
283 Scalar* dev_c, int ldc, int* dev_lapack_info) TF_MUST_USE_RESULT;
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| group-reloc-ldc-parsing-bad.s | 1 @ Tests for LDC group relocations that are meant to fail during parsing.
25 ldctest ldc c0
|
| group-reloc-ldc.d | 3 #name: Group relocation tests (ldc)
8 0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\].*
10 0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\].*
12 0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\].*
14 0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\].*
16 0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\].*
18 0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\].*
32 0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\].*
34 0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\].*
36 0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\].
[all...] |
| group-reloc-ldc-encoding-bad.s | 1 @ LDC group relocation tests that are supposed to fail during encoding.
5 @ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
43 ldctest ldc stc 0x1
48 ldctest ldc stc 0x808
|
| group-reloc-ldc-parsing-bad.l | 2 [^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
3 [^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
4 [^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
5 [^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
6 [^:]*:25: Error: unknown group relocation -- `ldc 0,c0,\[r0,#:foo:\(sym\)\]'
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/sh/ |
| sh2a.s | 47 ldc r3,tbr
|
| /external/gemmlowp/test/ |
| test.cc | 41 std::int32_t c_shift, int ldc) {
70 c_i_stride = ldc;
74 c_j_stride = ldc;
766 const int ldc = m; local
774 ldc);
956 const int ldc = m; local
1066 const int ldc = m; local
1144 const int ldc = n; local
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mep/ |
| allinsn.s | 706 .global ldc
707 ldc: label
708 ldc $tp,$lo
709 ldc $8,$npc
710 ldc $9,$mb0
711 ldc $15,$sar
712 ldc $9,$ccfg
1395 ldc $0, (4 + 4)
|
