| /external/llvm/test/MC/AArch64/ |
| ras-extension.s | 6 msr errselr_el1, x0
7 msr errselr_el1, x15
8 msr errselr_el1, x25
9 msr erxctlr_el1, x1
10 msr erxstatus_el1, x2
11 msr erxaddr_el1, x3
12 msr erxmisc0_el1, x4
13 msr erxmisc1_el1, x5
14 msr disr_el1, x6
15 msr vdisr_el2, x
[all...] |
| trace-regs.s | 420 msr trcoslar, x28
421 msr trclar, x14
422 msr trcprgctlr, x10
423 msr trcprocselr, x27
424 msr trcconfigr, x24
425 msr trcauxctlr, x8
426 msr trceventctl0r, x16
427 msr trceventctl1r, x27
428 msr trcstallctlr, x26
429 msr trctsctlr, x
[all...] |
| gicv3-regs-diagnostics.s | 30 msr icc_iar1_el1, x16
31 msr icc_iar0_el1, x19
32 msr icc_hppir1_el1, x29
33 msr icc_hppir0_el1, x14
34 msr icc_rpr_el1, x6
35 msr ich_vtr_el2, x8
36 msr ich_eisr_el2, x22
37 msr ich_elsr_el2, x8
39 // CHECK-NEXT: msr icc_iar1_el1, x16
42 // CHECK-NEXT: msr icc_iar0_el1, x1
[all...] |
| armv8.1a-lor.s | 25 msr LORSA_EL1, x0
26 msr LOREA_EL1, x0
27 msr LORN_EL1, x0
28 msr LORC_EL1, x0
30 // CHECK: msr LORSA_EL1, x0 // encoding: [0x00,0xa4,0x18,0xd5]
31 // CHECK: msr LOREA_EL1, x0 // encoding: [0x20,0xa4,0x18,0xd5]
32 // CHECK: msr LORN_EL1, x0 // encoding: [0x40,0xa4,0x18,0xd5]
33 // CHECK: msr LORC_EL1, x0 // encoding: [0x60,0xa4,0x18,0xd5]
41 msr LORSA_EL1, #0
42 msr LOREA_EL1, #
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| armv7-a+virt.s | 41 msr R8_usr, r1
42 msr R9_usr, r1
43 msr R10_usr, r1
44 msr R11_usr, r1
45 msr R12_usr, r1
46 msr SP_usr, r1
47 msr LR_usr, r1
48 msr R8_fiq, r1
49 msr R9_fiq, r1
50 msr R10_fiq, r
[all...] |
| mrs-msr-thumb-v6t2.s | 8 msr apsr_nzcvqg, r4
9 msr cpsr_f, r5
10 msr spsr, r6
|
| mrs-msr-thumb-v7e-m.s | 8 msr apsr_nzcvqg, r4
9 msr iapsr_g, r5
10 msr basepri_max, r6
|
| mrs-msr-arm-v7-a-bad.s | 7 msr iapsr, r4
8 msr apsr, r5
|
| arch4t.s | 22 msr CPSR_f, #2
23 msr CPSR_c, r3
24 msr CPSR_x, r4
25 msr CPSR_s, r5
26 msr CPSR_f, r6
27 msr CPSR_all, r7
29 msr SPSR_f, #4
30 msr SPSR_c, r8
31 msr SPSR_x, r9
32 msr SPSR_s, r1
[all...] |
| mrs-msr-arm-v6.d | 2 #name: MRS/MSR test, architecture v6, ARM mode
11 0+0c <[^>]*> e328f101 msr CPSR_f, #1073741824 ; 0x40000000
12 0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
13 0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
14 0+18 <[^>]*> e128f004 msr CPSR_f, r4
15 0+1c <[^>]*> e128f005 msr CPSR_f, r5
16 0+20 <[^>]*> e169f006 msr SPSR_fc, r6
|
| mrs-msr-arm-v7-a.d | 2 #name: MRS/MSR test, architecture v7-A, ARM mode
11 0+0c <[^>]*> e32cf101 msr CPSR_fs, #1073741824 ; 0x40000000
12 0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
13 0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
14 0+18 <[^>]*> e128f004 msr CPSR_f, r4
15 0+1c <[^>]*> e128f005 msr CPSR_f, r5
16 0+20 <[^>]*> e169f006 msr SPSR_fc, r6
|
| archv8m-cmse-msr-base.d | 1 #name: ARMv8-M Baseline Security Extensions MSR/MRS instructions
2 #source: archv8m-cmse-msr.s
9 0+.* <[^>]*> f380 8808 msr MSP, r0
10 0+.* <[^>]*> f380 8888 msr MSP_NS, r0
11 0+.* <[^>]*> f380 8809 msr PSP, r0
12 0+.* <[^>]*> f380 8889 msr PSP_NS, r0
13 0+.* <[^>]*> f380 8808 msr MSP, r0
14 0+.* <[^>]*> f380 8888 msr MSP_NS, r0
15 0+.* <[^>]*> f380 8809 msr PSP, r0
16 0+.* <[^>]*> f380 8889 msr PSP_NS, r
[all...] |
| archv8m-cmse-msr-main.d | 1 #name: ARMv8-M Mainline Security Extensions MSR/MRS instructions
2 #source: archv8m-cmse-msr.s
9 0+.* <[^>]*> f380 8808 msr MSP, r0
10 0+.* <[^>]*> f380 8888 msr MSP_NS, r0
11 0+.* <[^>]*> f380 8809 msr PSP, r0
12 0+.* <[^>]*> f380 8889 msr PSP_NS, r0
13 0+.* <[^>]*> f380 8808 msr MSP, r0
14 0+.* <[^>]*> f380 8888 msr MSP_NS, r0
15 0+.* <[^>]*> f380 8809 msr PSP, r0
16 0+.* <[^>]*> f380 8889 msr PSP_NS, r
[all...] |
| archv8m-main-dsp-4.d | 2 #source: archv8m-cmse-msr.s
9 0+.* <[^>]*> f380 8808 msr MSP, r0
10 0+.* <[^>]*> f380 8888 msr MSP_NS, r0
11 0+.* <[^>]*> f380 8809 msr PSP, r0
12 0+.* <[^>]*> f380 8889 msr PSP_NS, r0
13 0+.* <[^>]*> f380 8808 msr MSP, r0
14 0+.* <[^>]*> f380 8888 msr MSP_NS, r0
15 0+.* <[^>]*> f380 8809 msr PSP, r0
16 0+.* <[^>]*> f380 8889 msr PSP_NS, r0
|
| arch4t-eabi.d | 26 0+38 <[^>]+> e328f002 ? msr CPSR_f, #2
27 0+3c <[^>]+> e121f003 ? msr CPSR_c, r3
28 0+40 <[^>]+> e122f004 ? msr CPSR_x, r4
29 0+44 <[^>]+> e124f005 ? msr CPSR_s, r5
30 0+48 <[^>]+> e128f006 ? msr CPSR_f, r6
31 0+4c <[^>]+> e129f007 ? msr CPSR_fc, r7
32 0+50 <[^>]+> e368f004 ? msr SPSR_f, #4
33 0+54 <[^>]+> e161f008 ? msr SPSR_c, r8
34 0+58 <[^>]+> e162f009 ? msr SPSR_x, r9
35 0+5c <[^>]+> e164f00a ? msr SPSR_s, s
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| sysreg-1.d | 11 c: d51b4527 msr dlr_el0, x7
13 14: d51b4507 msr dspsr_el0, x7
15 1c: d51e1127 msr sder32_el3, x7
17 24: d51e1327 msr mdcr_el3, x7
19 2c: d5100207 msr mdccint_el1, x7
21 34: d5140707 msr dbgvcr32_el2, x7
23 3c: d51c5307 msr fpexc32_el2, x7
25 44: d5120007 msr teecr32_el1, x7
27 4c: d5121007 msr teehbr32_el1, x7
29 54: d51be207 msr cntp_tval_el0, x
[all...] |
| pan-illegal.l | 2 [^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr pan,#2'
3 [^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr pan,#3'
4 [^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr pan,#4'
5 [^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr pan,#5'
6 [^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr pan,#6'
7 [^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr pan,#7'
8 [^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr pan,#8'
9 [^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr pan,#9'
10 [^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr pan,#10'
11 [^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr pan,#11
[all...] |
| armv8-ras-1.d | 12 [^:]+: d5185327 msr errselr_el1, x7
15 [^:]+: d5185425 msr erxctlr_el1, x5
17 [^:]+: d5185445 msr erxstatus_el1, x5
19 [^:]+: d5185465 msr erxaddr_el1, x5
21 [^:]+: d5185505 msr erxmisc0_el1, x5
23 [^:]+: d5185525 msr erxmisc1_el1, x5
26 [^:]+: d518c125 msr disr_el1, x5
32 [^:]+: d5185327 msr errselr_el1, x7
35 [^:]+: d5185425 msr erxctlr_el1, x5
37 [^:]+: d5185445 msr erxstatus_el1, x
[all...] |
| pan-directive.d | 10 0: d500419f msr pan, #0x1
11 4: d500409f msr pan, #0x0
12 8: d5184260 msr pan, x0
|
| pan.d | 9 0: d500419f msr pan, #0x1
10 4: d500409f msr pan, #0x0
11 8: d5184260 msr pan, x0
|
| uao-directive.d | 10 [0-9a-f]:+ d500417f msr uao, #0x1
11 [0-9a-f]:+ d500407f msr uao, #0x0
12 [0-9a-f]:+ d5184280 msr uao, x0
|
| uao.d | 9 [0-9a-f]:+ d500417f msr uao, #0x1
10 [0-9a-f]:+ d500407f msr uao, #0x0
11 [0-9a-f]:+ d5184280 msr uao, x0
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/ |
| GicV3.S | 40 msr scr_el3, x0
46 msr ICC_SRE_EL3, x1
52 msr ICC_SRE_EL2, x1
56 msr ICC_CTLR_EL3, xzr
58 msr ICC_CTLR_EL1, xzr
63 msr ICC_PMR_EL1, x1
69 msr scr_el3, x0
|
| /device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch32/ |
| smcc_macros.S | 86 msr sp_usr, r4
87 msr lr_usr, r5
88 msr spsr_irq, r6
89 msr sp_irq, r7
90 msr lr_irq, r8
91 msr spsr_fiq, r9
92 msr sp_fiq, r10
93 msr lr_fiq, r11
94 msr spsr_svc, r12
97 msr sp_svc, r
[all...] |
| /external/capstone/suite/MC/ARM/ |
| thumb2-mclass.s.cs | 16 0x80,0xf3,0x00,0x88 = msr apsr, r0
17 0x80,0xf3,0x00,0x88 = msr apsr, r0
18 0x80,0xf3,0x00,0x84 = msr apsr_g, r0
19 0x80,0xf3,0x00,0x8c = msr apsr_nzcvqg, r0
20 0x80,0xf3,0x01,0x88 = msr iapsr, r0
21 0x80,0xf3,0x01,0x88 = msr iapsr, r0
22 0x80,0xf3,0x01,0x84 = msr iapsr_g, r0
23 0x80,0xf3,0x01,0x8c = msr iapsr_nzcvqg, r0
24 0x80,0xf3,0x02,0x88 = msr eapsr, r0
25 0x80,0xf3,0x02,0x88 = msr eapsr, r
[all...] |
