| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-operand-rn-in-it-block-t32.cc | 107 {{eq, r0, r11}, true, eq, "eq r0 r11", "eq_r0_r11"},
122 {{eq, r1, r11}, true, eq, "eq r1 r11", "eq_r1_r11"},
137 {{eq, r2, r11}, true, eq, "eq r2 r11", "eq_r2_r11"},
152 {{eq, r3, r11}, true, eq, "eq r3 r11", "eq_r3_r11"},
167 {{eq, r4, r11}, true, eq, "eq r4 r11", "eq_r4_r11"}
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 136 {{al, r9, r10, r11, ROR, 2},
139 "al r9 r10 r11 ROR 2",
141 {{al, r14, r11, r5, LSL, 15},
144 "al r14 r11 r5 LSL 15",
151 {{al, r2, r11, r1, ROR, 9},
154 "al r2 r11 r1 ROR 9",
156 {{al, r11, r2, r8, LSL, 4},
159 "al r11 r2 r8 LSL 4",
181 {{al, r0, r2, r11, LSL, 10},
184 "al r0 r2 r11 LSL 10"
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 121 {{mi, r8, r11, r8, ASR, 32},
124 "mi r8 r11 r8 ASR 32",
176 {{pl, r13, r8, r11, ASR, 17},
179 "pl r13 r8 r11 ASR 17",
186 {{vc, r11, r2, r7, LSR, 30},
189 "vc r11 r2 r7 LSR 30",
196 {{cc, r11, r3, r0, LSR, 20},
199 "cc r11 r3 r0 LSR 20",
226 {{pl, r11, r1, r0, LSR, 14},
229 "pl r11 r1 r0 LSR 14"
[all...] |
| test-assembler-cond-rd-rn-operand-rm-t32.cc | 129 {{{al, r12, r9, r11}, false, al, "al r12 r9 r11", "al_r12_r9_r11"},
133 {{al, r11, r2, r4}, false, al, "al r11 r2 r4", "al_r11_r2_r4"},
135 {{al, r11, r6, r9}, false, al, "al r11 r6 r9", "al_r11_r6_r9"},
136 {{al, r8, r7, r11}, false, al, "al r8 r7 r11", "al_r8_r7_r11"},
144 {{al, r14, r7, r11}, false, al, "al r14 r7 r11", "al_r14_r7_r11"}
[all...] |
| test-assembler-cond-rd-rn-rm-t32.cc | 156 {{al, r11, r9, r0}, false, al, "al r11 r9 r0", "al_r11_r9_r0"},
162 {{al, r6, r12, r11}, false, al, "al r6 r12 r11", "al_r6_r12_r11"},
173 {{al, r13, r11, r3}, false, al, "al r13 r11 r3", "al_r13_r11_r3"},
182 {{al, r7, r11, r3}, false, al, "al r7 r11 r3", "al_r7_r11_r3"},
184 {{al, r1, r11, r6}, false, al, "al r1 r11 r6", "al_r1_r11_r6"}
[all...] |
| test-assembler-cond-rd-rn-operand-rm-a32.cc | 130 {{ge, r5, r11, r10}, false, al, "ge r5 r11 r10", "ge_r5_r11_r10"},
140 {{gt, r11, r1, r9}, false, al, "gt r11 r1 r9", "gt_r11_r1_r9"},
141 {{cc, r8, r6, r11}, false, al, "cc r8 r6 r11", "cc_r8_r6_r11"},
145 {{pl, r11, r8, r2}, false, al, "pl r11 r8 r2", "pl_r11_r8_r2"},
151 {{ls, r2, r11, r0}, false, al, "ls r2 r11 r0", "ls_r2_r11_r0"}
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 146 {{pl, r11, r1, r7, LSL, 23},
149 "pl r11 r1 r7 LSL 23",
206 {{ne, r8, r11, r14, ROR, 19},
209 "ne r8 r11 r14 ROR 19",
211 {{vc, r4, r11, r5, ROR, 15},
214 "vc r4 r11 r5 ROR 15",
226 {{gt, r11, r11, r8, LSL, 16},
229 "gt r11 r11 r8 LSL 16"
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 116 const TestData kTests[] = {{{al, r11, r13, r10, ASR, 9},
119 "al r11 r13 r10 ASR 9",
126 {{al, r5, r2, r11, LSR, 5},
129 "al r5 r2 r11 LSR 5",
166 {{al, r12, r11, r4, ASR, 7},
169 "al r12 r11 r4 ASR 7",
176 {{al, r2, r10, r11, ASR, 1},
179 "al r2 r10 r11 ASR 1",
186 {{al, r11, r6, r14, ASR, 31},
189 "al r11 r6 r14 ASR 31"
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_inter_pred_filters_luma_horz.s | 135 mov r11,#1
196 vld1.u32 {d0},[r12],r11 @vector load pu1_src
197 vld1.u32 {d1},[r12],r11
198 vld1.u32 {d2},[r12],r11
199 vld1.u32 {d3},[r12],r11
220 vld1.u32 {d4},[r12],r11
222 vld1.u32 {d5},[r12],r11
224 vld1.u32 {d6},[r12],r11
226 vld1.u32 {d7},[r12],r11
228 vld1.u32 {d12},[r4],r11 @vector load pu1_src + src_str
[all...] |
| ihevc_intra_pred_chroma_dc.s | 182 vmov.32 r11,d17[0]
185 add r11,r11,r4
188 lsr r11,r11,r12
191 vdup.8 d16,r11
198 moveq r11,r6
209 movne r11,#16
240 vst2.8 {d16,d17}, [r2],r11
241 vst2.8 {d16,d17}, [r5],r11
[all...] |
| /external/tremolo/Tremolo/ |
| mdctARM.s | 188 STMFD r13!,{r4,r6-r11,r14}
198 LDR r11,[r9],#4 @ r11= *wL++
203 SMULL r14,r11,r12,r11 @ (r14,r11) = *l * *wL++
205 ADD r6, r6, r11
216 LDMFD r13!,{r4,r6-r11,PC}
227 STMFD r13!,{r4,r6-r11,r14}
237 LDR r11,[r9],#4 @ r11= *wL+
[all...] |
| /external/libffi/src/s390/ |
| sysv.S | 52 lr %r11,%r15 # Set up frame pointer
59 l %r7,96(%r11) # Load function address
60 st %r11,0(%r15) # Set up back chain
61 ahi %r11,-48 # Register save area
68 lm %r2,%r6,0(%r11) # Load arguments
69 ld %f0,32(%r11)
70 ld %f2,40(%r11)
75 l %r4,48+56(%r11)
76 lm %r6,%r15,48+24(%r11)
80 l %r4,48+56(%r11)
[all...] |
| /external/python/cpython2/Modules/_ctypes/libffi/src/s390/ |
| sysv.S | 52 lr %r11,%r15 # Set up frame pointer
59 l %r7,96(%r11) # Load function address
60 st %r11,0(%r15) # Set up back chain
61 ahi %r11,-48 # Register save area
68 lm %r2,%r6,0(%r11) # Load arguments
69 ld %f0,32(%r11)
70 ld %f2,40(%r11)
75 l %r4,48+56(%r11)
76 lm %r6,%r15,48+24(%r11)
80 l %r4,48+56(%r11)
[all...] |
| /external/python/cpython3/Modules/_ctypes/libffi/src/s390/ |
| sysv.S | 52 lr %r11,%r15 # Set up frame pointer
59 l %r7,96(%r11) # Load function address
60 st %r11,0(%r15) # Set up back chain
61 ahi %r11,-48 # Register save area
68 lm %r2,%r6,0(%r11) # Load arguments
69 ld %f0,32(%r11)
70 ld %f2,40(%r11)
75 l %r4,48+56(%r11)
76 lm %r6,%r15,48+24(%r11)
80 l %r4,48+56(%r11)
[all...] |
| /external/webrtc/webrtc/modules/audio_coding/codecs/isac/fix/source/ |
| lattice_armv7.S | 26 @ r6, r7, r8, r10, r11: scratch
34 push {r4-r11}
55 smlabb r11, r7, r5, r12 @ sth_Q15[k - 1] * tmpAR + 16384
58 smlabb r11, r6, r8, r11 @ cth_Q15[k - 1] * ar_g_Q0[k - 1] +
63 ssat r11, #16, r11, asr #15
65 strh r11, [r0], #-2 @ Output: ar_g_Q0[k]
76 pop {r4-r11}
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| cor_h_vec_opt.s | 51 RSB r11, r2, #62 @j=62-pos
57 SUBS r11, r11, #1
74 LDRSH r11, [r9] @sign[pos + 1]
76 MUL r14, r6, r11
82 LDRSH r11, [r8] @*p3++
86 ADD r6, r6, r11
96 RSB r11, r2, #62 @j=62-pos
103 SUBS r11, r11, #
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| cor_h_vec_neon.s | 52 RSB r11, r2, #62 @j=62-pos
58 SUBS r11, r11, #1
75 LDRSH r11, [r9] @sign[pos + 1]
77 MUL r14, r6, r11
83 LDRSH r11, [r8] @*p3++
87 ADD r6, r6, r11
97 RSB r11, r2, #62 @j=62-pos
104 SUBS r11, r11, #
[all...] |
| /external/boringssl/win-x86_64/crypto/fipsmodule/ |
| x86_64-mont5.asm | 51 mov r11,rsp
64 sub r11,r10
65 and r11,-4096
66 lea rsp,[r11*1+r10]
67 mov r11,QWORD[rsp]
74 mov r11,QWORD[rsp]
227 mov r11,rdx
243 add r13,r11
244 mov r11,r10
251 add r11,ra
[all...] |
| /device/linaro/bootloader/edk2/ArmVirtPkg/PrePi/Arm/ |
| ModuleEntryPoint.S | 104 adds r11, r1, #1
108 mov r1, r11
114 MOV32 (r11, (~EFI_PAGE_MASK) & 0xffffffff)
115 and r1, r1, r11
119 sub r11, r1, r4
147 mov r1, r11
|
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-x86-64/ |
| pr19609-1a.d | 14 [ ]*[a-f0-9]+: 49 81 fb 00 00 00 00 cmp \$0x0,%r11
18 [ ]*[a-f0-9]+: 49 c7 c3 00 00 00 00 mov \$0x0,%r11
22 [ ]*[a-f0-9]+: 49 f7 c3 00 00 00 00 test \$0x0,%r11
|
| pr19609-1b.d | 14 [ ]*[a-f0-9]+: 49 81 fb 00 00 00 00 cmp \$0x0,%r11
18 [ ]*[a-f0-9]+: 49 c7 c3 00 00 00 00 mov \$0x0,%r11
22 [ ]*[a-f0-9]+: 49 f7 c3 00 00 00 00 test \$0x0,%r11
|
| pr19609-1d.d | 14 [ ]*[a-f0-9]+: 49 81 fb 00 00 00 00 cmp \$0x0,%r11
18 [ ]*[a-f0-9]+: 49 c7 c3 00 00 00 00 mov \$0x0,%r11
22 [ ]*[a-f0-9]+: 49 f7 c3 00 00 00 00 test \$0x0,%r11
|
| pr19609-1f.d | 14 [ ]*[a-f0-9]+: 49 81 fb 00 00 00 00 cmp \$0x0,%r11
18 [ ]*[a-f0-9]+: 49 c7 c3 00 00 00 00 mov \$0x0,%r11
22 [ ]*[a-f0-9]+: 49 f7 c3 00 00 00 00 test \$0x0,%r11
|
| pr19609-1g.d | 14 [ ]*[a-f0-9]+: 49 81 fb 00 00 00 00 cmp \$0x0,%r11
18 [ ]*[a-f0-9]+: 49 c7 c3 00 00 00 00 mov \$0x0,%r11
22 [ ]*[a-f0-9]+: 49 f7 c3 00 00 00 00 test \$0x0,%r11
|
| pr19609-1k.d | 14 [ ]*[a-f0-9]+: 49 81 fb 00 00 00 00 cmp \$0x0,%r11
18 [ ]*[a-f0-9]+: 49 c7 c3 00 00 00 00 mov \$0x0,%r11
22 [ ]*[a-f0-9]+: 49 f7 c3 00 00 00 00 test \$0x0,%r11
|
