| /external/libdrm/nouveau/ |
| nouveau.h | 103 uint32_t tile_mode; member in struct:nouveau_bo_config::__anon24678
107 uint32_t tile_mode; member in struct:nouveau_bo_config::__anon24679
|
| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| nvc0_video_bsp.c | 71 cfg.nvc0.tile_mode = 0x10;
107 cfg.nvc0.tile_mode = 0x10;
|
| nvc0_tex.c | 161 ((mt->level[0].tile_mode & 0x0f0) >> 4 << 3) |
162 ((mt->level[0].tile_mode & 0xf00) >> 8 << 6);
368 ((mt->level[0].tile_mode & 0x0f0) << (22 - 4)) |
369 ((mt->level[0].tile_mode & 0xf00) << (25 - 8));
932 info[4] |= (lvl->tile_mode & 0x0f0) << 25;
933 info[4] |= NVC0_TILE_SHIFT_Y(lvl->tile_mode) << 22;
936 info[6] |= (lvl->tile_mode & 0xf00) << 21;
937 info[6] |= NVC0_TILE_SHIFT_Z(lvl->tile_mode) << 22;
[all...] |
| nvc0_transfer.c | 39 PUSH_DATA (push, src->tile_mode);
55 PUSH_DATA (push, dst->tile_mode);
143 PUSH_DATA (push, 0x1000 | dst->tile_mode);
151 PUSH_DATA (push, 0x1000 | src->tile_mode);
|
| nvc0_video.c | 99 cfg.nvc0.tile_mode = 0x10;
|
| nvc0_state_validate.c | 117 mt->level[sf->base.u.tex.level].tile_mode);
160 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
|
| nvc0_surface.c | 131 PUSH_DATA (push, mt->level[level].tile_mode);
321 mt->level[sf->base.u.tex.level].tile_mode);
663 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
[all...] |
| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| radv_amdgpu_surface.c | 269 uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]]; local
272 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
274 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
|
| /external/libdrm/libkms/ |
| nouveau.c | 113 arg.info.tile_mode = 0;
|
| /external/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| fd5_gmem.c | 49 enum a5xx_tile_mode tile_mode; local
53 tile_mode = TILE5_2;
55 tile_mode = TILE5_LINEAR;
97 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
|
| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| nv50_transfer.c | 41 rect->tile_mode = mt->level[l].tile_mode;
79 PUSH_DATA (push, src->tile_mode);
96 PUSH_DATA (push, dst->tile_mode);
|
| nv50_tex.c | 157 ((mt->level[0].tile_mode & 0x0f0) << (22 - 4)) |
158 ((mt->level[0].tile_mode & 0xf00) << (25 - 8));
|
| nv50_state_validate.c | 64 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
105 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
|
| nv84_video.c | 480 mip.level[0].tile_mode = 0;
659 cfg.nv50.tile_mode = 0x20;
|
| nv50_surface.c | 128 PUSH_DATA (push, mt->level[level].tile_mode);
317 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
414 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| cik_sdma.c | 125 unsigned tile_mode = info->si_tile_mode_array[tile_index]; local
129 (G_009910_ARRAY_MODE(tile_mode) << 3) |
130 (G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) |
137 (G_009910_PIPE_CONFIG(tile_mode) << 26);
|
| si_state.c | 2237 unsigned tile_mode = info->si_tile_mode_array[index]; local
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/sysroot/usr/include/drm/ |
| nouveau_drm.h | 110 uint32_t tile_mode; member in struct:drm_nouveau_gem_info
|
| /cts/hostsidetests/security/securityPatch/CVE-2017-6262/ |
| local_poc.h | 106 uint32_t tile_mode; member in struct:drm_nouveau_gem_info
116 uint32_t tile_mode; member in struct:drm_nouveau_gem_map
|
| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| amdgpu_surface.c | 278 uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]]; local
281 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
283 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
|
| /external/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
| fd4_gmem.c | 52 enum a4xx_tile_mode tile_mode; local
56 tile_mode = 2;
58 tile_mode = TILE4_LINEAR;
116 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
|
| /external/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
| fd3_gmem.c | 51 enum a3xx_tile_mode tile_mode; local
55 tile_mode = TILE_32X32;
57 tile_mode = LINEAR;
113 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
[all...] |
| /hardware/qcom/media/msm8996/libc2dcolorconvert/ |
| C2DColorConverter.cpp | 493 int32_t tile_mode = 0; local
501 mAdrenoComputeAlignedWidthAndHeight(width, height, bpp, tile_mode, raster_mode, padding_threshold,
508 mAdrenoComputeAlignedWidthAndHeight(width, height, bpp, tile_mode, raster_mode, padding_threshold,
|
| /hardware/qcom/media/msm8998/libc2dcolorconvert/ |
| C2DColorConverter.cpp | 499 int32_t tile_mode = 0; local
507 mAdrenoComputeAlignedWidthAndHeight(width, height, bpp, tile_mode, raster_mode, padding_threshold,
514 mAdrenoComputeAlignedWidthAndHeight(width, height, bpp, tile_mode, raster_mode, padding_threshold,
|
| /external/mesa3d/src/amd/vulkan/ |
| radv_device.c | 1782 unsigned tile_mode = info->si_tile_mode_array[tiling_index]; local
[all...] |
