| /external/swiftshader/third_party/subzero/crosstest/ |
| test_bitmanip.cpp | 21 #define X(inst, type) \
22 type test_##inst(type a) { return my_##inst(a); } \
23 type test_alloca_##inst(type a) { \
27 buf[i] = my_##inst(a); \
35 type test_const_##inst(type ignored) { \
36 return my_##inst(static_cast<type>(0x12340)); \
|
| /prebuilts/ndk/r16/sources/third_party/shaderc/third_party/spirv-tools/source/opt/ |
| def_use_manager.h | 35 ir::Instruction* inst; // Instruction using the id. member in struct:spvtools::opt::analysis::Use
62 // Analyzes the defs in the given |inst|.
63 void AnalyzeInstDef(ir::Instruction* inst);
65 // Analyzes the uses in the given |inst|.
66 void AnalyzeInstUse(ir::Instruction* inst);
68 // Analyzes the defs and uses in the given |inst|.
69 void AnalyzeInstDefUse(ir::Instruction* inst);
95 // Turns the given instruction |inst| to a Nop. This method erases the
96 // information of the given instruction's uses of its operands. If |inst|
98 void KillInst(ir::Instruction* inst);
[all...] |
| eliminate_dead_constant_pass.cpp | 42 return !(ir::IsAnnotationInst(u.inst->opcode()) ||
43 ir::IsDebugInst(u.inst->opcode()));
56 ir::Instruction* inst = *working_list.begin(); local
58 switch (inst->opcode()) {
62 for (uint32_t i = 0; i < inst->NumInOperands(); i++) {
65 if (inst->GetInOperand(i).type != SPV_OPERAND_TYPE_ID) {
68 uint32_t operand_id = inst->GetSingleWordInOperand(i);
87 dead_consts.insert(inst);
88 working_list.erase(inst);
97 if (ir::IsAnnotationInst(u.inst->opcode()) |
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| neon-vfp-reglist-post.s | 9 .macro ldst1_reg_list_post_imm_64 inst type
10 \inst\()1 {v0.\type}, [x0], #8
11 \inst\()1 {v0.\type, v1.\type}, [x0], #16
12 \inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #24
13 \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
22 .macro ldst1_reg_list_post_imm_128 inst type
23 \inst\()1 {v0.\type}, [x0], #16
24 \inst\()1 {v0.\type, v1.\type}, [x0], #32
25 \inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #48
26 \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #6
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow.c | 65 struct rc_pair_instruction * inst,
76 inst->RGB.Src[src].Index);
90 inst->Alpha.Src[src].Index);
103 struct rc_pair_instruction * inst = &fullinst->U.P; local
112 GET_SWZ(inst->RGB.Arg[arg].Swizzle, chan);
114 GET_SWZ(inst->Alpha.Arg[arg].Swizzle, chan);
115 pair_get_src_refmasks(refmasks, inst, swz_rgb,
116 inst->RGB.Arg[arg].Source);
117 pair_get_src_refmasks(refmasks, inst, swz_alpha,
118 inst->Alpha.Arg[arg].Source)
258 struct rc_sub_instruction * inst = &fullinst->U.I; local
270 struct rc_pair_instruction * inst = &fullinst->U.P; local
343 struct rc_sub_instruction * inst = &fullinst->U.I; local
392 struct rc_pair_instruction * inst = &fullinst->U.P; local
[all...] |
| radeon_remove_constants.c | 37 static void remap_regs(void * userdata, struct rc_instruction * inst,
47 static void mark_used(void * userdata, struct rc_instruction * inst,
86 for (struct rc_instruction *inst = c->Program.Instructions.Next;
87 inst != &c->Program.Instructions; inst = inst->Next) {
88 rc_for_all_reads_src(inst, mark_used, &d);
128 for (struct rc_instruction *inst = c->Program.Instructions.Next;
129 inst != &c->Program.Instructions; inst = inst->Next)
[all...] |
| r300_fragprog.c | 34 static void presub_string(char out[10], unsigned int inst)
36 switch(inst & 0x600000){
94 inst[i] >> R300_TEX_INST_SHIFT) &
116 inst[i] >> R300_DST_ADDR_SHIFT) & 31,
119 inst[i] >> R300_SRC_ADDR_SHIFT) & 31,
121 inst[i] & R300_TEX_ID_MASK) >>
123 code->tex.inst[i]);
136 int regc = code->alu.inst[i].rgb_addr >> (j * 6);
137 int rega = code->alu.inst[i].alpha_addr >> (j * 6);
139 code->alu.inst[i].r400_ext_addr)
[all...] |
| radeon_emulate_loops.c | 89 static void update_const_value(void * data, struct rc_instruction * inst,
98 switch(inst->U.I.Opcode){
100 if(!rc_src_reg_is_immediate(value->C, inst->U.I.SrcReg[0].File,
101 inst->U.I.SrcReg[0].Index)){
107 inst->U.I.SrcReg[0].Index,
108 inst->U.I.SrcReg[0].Swizzle,
109 inst->U.I.SrcReg[0].Negate, 0);
114 static void get_incr_amount(void * data, struct rc_instruction * inst,
136 opcode = rc_get_opcode_info(inst->U.I.Opcode);
141 if(inst->U.I.SrcReg[0].File == RC_FILE_TEMPORARY &
196 struct rc_instruction * inst; local
504 struct rc_instruction * inst; local
[all...] |
| radeon_program_tex.c | 58 struct rc_instruction *inst,
65 inst_mov = rc_insert_new_instruction(&compiler->Base, inst->Prev);
70 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
74 state_constant, inst->U.I.TexSrcUnit);
76 reset_srcreg(&inst->U.I.SrcReg[0]);
77 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
78 inst->U.I.SrcReg[0].Index = temp;
82 struct rc_instruction *inst)
88 inst_rcp = rc_insert_new_instruction(&compiler->Base, inst->Prev);
93 inst_rcp->U.I.SrcReg[0] = inst->U.I.SrcReg[0]
[all...] |
| /external/llvm/test/MC/ARM/ |
| inst-directive-emit.s | 10 .inst.w 0xf2400000, 0xf2c00000
18 @ CHECK: inst.w 0xf2400000
19 @ CHECK: inst.w 0xf2c00000
|
| inst-thumb-overflow.s | 11 .inst.n 1 << 31
12 @ CHECK-ERROR: inst.n operand is too big, use inst.w instead
|
| inst-thumb-suffixes.s | 11 .inst 0x0000
12 @ CHECK-ERROR: cannot determine Thumb instruction size, use inst.n/inst.w instead
|
| /frameworks/rs/rsov/compiler/spirit/ |
| instructions.cpp | 26 IdRef::IdRef(Instruction *inst) : mId(inst->getId()), mInstruction(inst) {}
|
| /toolchain/binutils/binutils-2.27/opcodes/ |
| mcore-dis.c | 98 unsigned short inst; local
113 inst = (ibytes[0] << 8) | ibytes[1];
115 inst = (ibytes[1] << 8) | ibytes[0];
121 if (mcore_table[i].inst == (inst & imsk[mcore_table[i].opclass]))
125 (*print_func) (stream, ".short 0x%04x", inst);
128 const char *name = grname[inst & 0x0F];
138 (*print_func) (stream, "\t%d", inst & 0x3);
148 (*print_func) (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]);
157 (*print_func) (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF])
[all...] |
| /external/mesa3d/src/mesa/state_tracker/ |
| st_atifs_to_tgsi.c | 349 const struct atifs_instruction *inst)
358 unsigned dstreg = inst->DstReg[optype].Index - GL_REG_0_ATI;
360 if (!inst->Opcode[optype])
363 desc = &inst_desc[inst->Opcode[optype] - GL_MOV_ATI];
367 if (arg >= inst->ArgCount[optype]) {
373 &inst->SrcReg[optype][arg]);
383 GLuint dstMask = inst->DstReg[optype].dstMask;
394 emit_dstmod(t, *dst, inst->DstReg[optype].dstMod);
517 struct atifs_instruction *inst = &atifs->Instructions[pass][i]; local
518 compile_instruction(t, inst);
579 struct atifs_instruction *inst = &atifs->Instructions[pass][i]; local
693 struct tgsi_full_instruction inst; local
[all...] |
| st_cb_drawpixels_shader.c | 56 set_src(struct tgsi_full_instruction *inst, unsigned i, unsigned file, unsigned index,
59 inst->Src[i].Register.File = file;
60 inst->Src[i].Register.Index = index;
61 inst->Src[i].Register.SwizzleX = x;
62 inst->Src[i].Register.SwizzleY = y;
63 inst->Src[i].Register.SwizzleZ = z;
64 inst->Src[i].Register.SwizzleW = w;
67 #define SET_SRC(inst, i, file, index, x, y, z, w) \
68 set_src(inst, i, file, index, TGSI_SWIZZLE_##x, TGSI_SWIZZLE_##y, \
160 struct tgsi_full_instruction inst; local
[all...] |
| /external/mesa3d/src/gallium/drivers/vc4/ |
| vc4_qir_schedule.c | 45 struct qinst *inst; member in struct:schedule_node
182 struct qinst *inst = n->inst; local
190 for (int i = 0; i < qir_get_nsrc(inst); i++) {
191 switch (inst->src[i].file) {
194 state->last_temp_write[inst->src[i].index], n);
210 switch (inst->op) {
253 switch (inst->dst.file) {
259 add_write_dep(dir, &state->last_temp_write[inst->dst.index], n);
285 if (qir_depends_on_flags(inst))
304 struct qinst *inst = n->inst; local
642 struct qinst *inst = chosen->inst; local
[all...] |
| vc4_qir_emit_uniform_stream_resets.c | 41 qir_for_each_inst(inst, block) {
42 if (qir_has_uniform_read(inst))
82 qir_for_each_inst(inst, block) {
83 if (qir_has_uniform_read(inst))
|
| /external/mesa3d/src/mesa/program/ |
| prog_optimize.c | 54 get_src_arg_mask(const struct prog_instruction *inst,
60 assert(arg < _mesa_num_inst_src_regs(inst->Opcode));
63 switch (inst->Opcode) {
79 channel_mask = inst->DstReg.WriteMask & dst_mask;
107 const GLuint coord = GET_SWZ(inst->SrcReg[arg].Swizzle, comp);
214 struct prog_instruction *inst = prog->arb.Instructions + i; local
215 const GLuint numSrc = _mesa_num_inst_src_regs(inst->Opcode);
218 if (inst->SrcReg[j].File == file) {
219 GLuint index = inst->SrcReg[j].Index;
221 inst->SrcReg[j].Index = map[index]
258 const struct prog_instruction *inst = prog->arb.Instructions + i; local
301 struct prog_instruction *inst = prog->arb.Instructions + i; local
369 const struct prog_instruction *inst = prog->arb.Instructions + i; local
581 const struct prog_instruction *inst = prog->arb.Instructions + i; local
973 const struct prog_instruction *inst = instructions + i; local
1262 struct prog_instruction *inst = program->arb.Instructions + i; local
[all...] |
| /art/compiler/dex/ |
| dex_to_dex_compiler.cc | 75 void CompileReturnVoid(Instruction* inst, uint32_t dex_pc);
79 // the given "inst".
80 Instruction* CompileCheckCast(Instruction* inst, uint32_t dex_pc);
88 void CompileInstanceFieldAccess(Instruction* inst, uint32_t dex_pc,
97 void CompileInvokeVirtual(Instruction* inst, uint32_t dex_pc,
104 uint16_t GetIndexForInstruction(const Instruction* inst, uint32_t index);
193 uint16_t DexToDexCompiler::CompilationState::GetIndexForInstruction(const Instruction* inst,
196 return inst->IsQuickened() ? NextIndex() : index;
198 DCHECK(!inst->IsQuickened());
214 Instruction* inst = const_cast<Instruction*>(&it.Inst()) local
365 const Instruction& inst = instructions.InstructionAt(info.dex_pc); local
[all...] |
| /external/mesa3d/src/gallium/drivers/vc4/kernel/ |
| vc4_validate_shaders.c | 113 raddr_add_a_to_live_reg_index(uint64_t inst)
115 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
116 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
117 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
118 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
183 uint64_t inst = validation_state->shader[validation_state->ip]; local
185 QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
186 QPU_GET_FIELD(inst, QPU_WADDR_ADD));
187 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
188 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B)
307 uint64_t inst = validation_state->shader[validation_state->ip]; local
380 uint64_t inst = validation_state->shader[validation_state->ip]; local
471 uint64_t inst = validation_state->shader[validation_state->ip]; local
546 uint64_t inst = validation_state->shader[validation_state->ip]; local
593 uint64_t inst = validation_state->shader[validation_state->ip]; local
632 uint64_t inst = validation_state->shader[ip]; local
798 uint64_t inst = validation_state.shader[ip]; local
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_visitor.cpp | 65 vec4_visitor::emit(vec4_instruction *inst)
67 inst->ir = this->base_ir;
68 inst->annotation = this->current_annotation;
70 this->instructions.push_tail(inst);
72 return inst;
76 vec4_visitor::emit_before(bblock_t *block, vec4_instruction *inst,
79 new_inst->ir = inst->ir;
80 new_inst->annotation = inst->annotation;
82 inst->insert_before(block, new_inst);
84 return inst;
195 vec4_instruction *inst; local
210 vec4_instruction *inst; local
231 vec4_instruction *inst; local
257 vec4_instruction *inst; local
271 vec4_instruction *inst; local
535 vec4_instruction *inst = emit(MOV(saturated, src0)); local
724 vec4_instruction *inst = emit(BRW_OPCODE_SEL, dst, src0, src1); local
853 vec4_instruction *inst = local
957 vec4_instruction *inst = new(mem_ctx) vec4_instruction(opcode, dest); local
1234 vec4_instruction *inst; local
1422 vec4_instruction *inst = emit_urb_write_opcode(complete); local
1745 block, inst); local
[all...] |
| brw_fs_combine_constants.cpp | 48 could_coissue(const struct gen_device_info *devinfo, const fs_inst *inst)
53 switch (inst->opcode) {
68 must_promote_imm(const struct gen_device_info *devinfo, const fs_inst *inst)
70 switch (inst->opcode) {
109 fs_inst *inst; member in struct:imm
210 foreach_block_and_inst(block, fs_inst, inst, cfg) {
213 if (!could_coissue(devinfo, inst) && !must_promote_imm(devinfo, inst))
216 for (int i = 0; i < inst->sources; i++) {
217 if (inst->src[i].file != IMM |
[all...] |
| /art/runtime/interpreter/ |
| interpreter_intrinsics.h | 34 const Instruction* inst,
|
| /device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Demo/metaclasses/ |
| Trace.py | 47 inst = TracingInstance()
48 inst.__meta_init__(self)
50 init = inst.__getattr__('__init__')
54 return inst
83 def __init__(self, name, func, inst):
86 self.inst = inst
88 return apply(self.func, (self.inst,) + args, kw)
92 self.inst.__trace_call__(self.inst.__trace_output__,
[all...] |
