| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiMCCodeEmitter.cpp | 52 uint64_t getBinaryCodeForInstr(const MCInst &Inst,
58 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
62 unsigned getRiMemoryOpValue(const MCInst &Inst, unsigned OpNo,
66 unsigned getRrMemoryOpValue(const MCInst &Inst, unsigned OpNo,
70 unsigned getSplsOpValue(const MCInst &Inst, unsigned OpNo,
74 unsigned getBranchTargetOpValue(const MCInst &Inst, unsigned OpNo,
78 unsigned getCallTargetOpValue(const MCInst &Inst, unsigned OpNo,
82 void encodeInstruction(const MCInst &Inst, raw_ostream &Ostream,
86 unsigned adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
89 unsigned adjustPqBitsSpls(const MCInst &Inst, unsigned Value
[all...] |
| /external/llvm/lib/Analysis/ |
| OrderedBasicBlock.cpp | 37 const Instruction *Inst = nullptr;
49 Inst = cast<Instruction>(II);
50 NumberedInsts[Inst] = NextInstPos++;
51 if (Inst == A || Inst == B)
56 assert((Inst == A || Inst == B) && "Should find A or B");
58 return Inst == A;
|
| Delinearization.cpp | 72 static Value *getPointerOperand(Instruction &Inst) {
73 if (LoadInst *Load = dyn_cast<LoadInst>(&Inst))
75 else if (StoreInst *Store = dyn_cast<StoreInst>(&Inst))
77 else if (GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(&Inst))
85 Instruction *Inst = &(*I);
88 if (!isa<StoreInst>(Inst) && !isa<LoadInst>(Inst) &&
89 !isa<GetElementPtrInst>(Inst))
92 const BasicBlock *BB = Inst->getParent();
96 const SCEV *AccessFn = SE->getSCEVAtScope(getPointerOperand(*Inst), L)
[all...] |
| PHITransAddr.cpp | 25 static bool CanPHITrans(Instruction *Inst) {
26 if (isa<PHINode>(Inst) ||
27 isa<GetElementPtrInst>(Inst))
30 if (isa<CastInst>(Inst) &&
31 isSafeToSpeculativelyExecute(Inst))
34 if (Inst->getOpcode() == Instruction::Add &&
35 isa<ConstantInt>(Inst->getOperand(1)))
118 Instruction *Inst = dyn_cast<Instruction>(Addr);
119 return !Inst || CanPHITrans(Inst);
[all...] |
| MemDepPrinter.cpp | 73 static InstTypePair getInstTypePair(const Instruction* inst, DepType type) {
74 return InstTypePair(inst, type);
100 Instruction *Inst = &I;
102 if (!Inst->mayReadFromMemory() && !Inst->mayWriteToMemory())
105 MemDepResult Res = MDA.getDependency(Inst);
107 Deps[Inst].insert(std::make_pair(getInstTypePair(Res),
109 } else if (auto CS = CallSite(Inst)) {
113 DepSet &InstDeps = Deps[Inst];
120 assert( (isa<LoadInst>(Inst) || isa<StoreInst>(Inst) |
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| EarlyCSE.cpp | 55 Instruction *Inst;
57 SimpleValue(Instruction *I) : Inst(I) {
58 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!");
62 return Inst == DenseMapInfo<Instruction *>::getEmptyKey() ||
63 Inst == DenseMapInfo<Instruction *>::getTombstoneKey();
66 static bool canHandle(Instruction *Inst) {
68 if (CallInst *CI = dyn_cast<CallInst>(Inst))
70 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) ||
71 isa<GetElementPtrInst>(Inst) || isa<CmpInst>(Inst) |
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| InstrInfoEmitter.cpp | 52 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
55 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
64 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
68 OperandList.push_back(Inst.Operands[i]);
70 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
71 OperandList.push_back(Inst.Operands[i]);
101 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
106 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
113 Inst.Operands[i].Constraints[j];
126 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.")
[all...] |
| /external/capstone/arch/Mips/ |
| MipsDisassembler.c | 43 static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
46 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
49 static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
52 static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
55 static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
58 static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
61 static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
64 static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
67 static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
70 static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceInstrumentation.cpp | 61 Inst *Instr = iteratorToInst(Context.getCur());
63 case Inst::Alloca:
66 case Inst::Arithmetic:
69 case Inst::Br:
72 case Inst::Call:
75 case Inst::Cast:
78 case Inst::ExtractElement:
81 case Inst::Fcmp:
84 case Inst::Icmp:
87 case Inst::InsertElement
[all...] |
| /external/llvm/lib/Transforms/ObjCARC/ |
| DependencyAnalysis.h | 62 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg,
67 bool CanUse(const Instruction *Inst, const Value *Ptr, ProvenanceAnalysis &PA,
72 bool CanAlterRefCount(const Instruction *Inst, const Value *Ptr,
75 /// Returns true if we can not conservatively prove that Inst can not decrement
77 bool CanDecrementRefCount(const Instruction *Inst, const Value *Ptr,
80 static inline bool CanDecrementRefCount(const Instruction *Inst,
83 return CanDecrementRefCount(Inst, Ptr, PA, GetARCInstKind(Inst));
|
| DependencyAnalysis.cpp | 35 bool llvm::objcarc::CanAlterRefCount(const Instruction *Inst, const Value *Ptr,
48 ImmutableCallSite CS(Inst);
56 const DataLayout &DL = Inst->getModule()->getDataLayout();
71 bool llvm::objcarc::CanDecrementRefCount(const Instruction *Inst,
80 return CanAlterRefCount(Inst, Ptr, PA, Class);
85 bool llvm::objcarc::CanUse(const Instruction *Inst, const Value *Ptr,
92 const DataLayout &DL = Inst->getModule()->getDataLayout();
96 if (const ICmpInst *ICI = dyn_cast<ICmpInst>(Inst)) {
102 } else if (auto CS = ImmutableCallSite(Inst)) {
112 } else if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
[all...] |
| ObjCARCExpand.cpp | 97 Instruction *Inst = &*I;
99 DEBUG(dbgs() << "ObjCARCExpand: Visiting: " << *Inst << "\n");
101 switch (GetBasicARCInstKind(Inst)) {
113 Value *Value = cast<CallInst>(Inst)->getArgOperand(0);
114 DEBUG(dbgs() << "ObjCARCExpand: Old = " << *Inst << "\n"
116 Inst->replaceAllUsesWith(Value);
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 192 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
194 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
351 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
352 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
354 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
355 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
396 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 33 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
36 static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst,
40 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
43 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
46 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
49 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
52 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
55 static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst,
58 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
61 static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst,
[all...] |
| /external/llvm/utils/TableGen/ |
| InstrInfoEmitter.cpp | 55 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
71 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
88 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
91 for (auto &Op : Inst.Operands) {
180 for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
181 std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
207 for (const CodeGenInstruction *Inst : NumberedInstructions) {
208 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
211 for (const auto &Info : Inst->Operands) {
220 OperandMap[OpList].push_back(Namespace + "::" + Inst->TheDef->getName())
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 651 inline static void addOps(MCInst &subInstPtr, MCInst const &Inst,
653 if (Inst.getOperand(opNum).isReg()) {
654 switch (Inst.getOperand(opNum).getReg()) {
682 subInstPtr.addOperand(Inst.getOperand(opNum));
686 subInstPtr.addOperand(Inst.getOperand(opNum));
689 MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {
693 switch (Inst.getOpcode()) {
695 // dbgs() << "opcode: "<< Inst->getOpcode() << "\n";
699 Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
703 addOps(Result, Inst, 0)
[all...] |
| /external/llvm/include/llvm/CodeGen/GlobalISel/ |
| IRTranslator.h | 73 /// Translate \p Inst into its corresponding MachineInstr instruction(s).
94 bool translate(const Instruction &Inst);
96 /// Translate \p Inst into a binary operation \p Opcode.
97 /// \pre \p Inst is a binary operation.
98 bool translateBinaryOp(unsigned Opcode, const Instruction &Inst);
101 /// \pre \p Inst is a branch instruction.
102 bool translateBr(const Instruction &Inst);
107 /// \pre \p Inst is a return instruction.
108 bool translateReturn(const Instruction &Inst);
150 // for each inst in b
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.h | 19 struct Inst {
21 Inst(unsigned Opc, unsigned ImmOpnd);
23 typedef SmallVector<Inst, 7 > InstSeq;
33 void AddInstr(InstSeqLs &SeqLs, const Inst &I);
|
| /external/capstone/arch/PowerPC/ |
| PPCDisassembler.c | 153 static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo,
157 MCOperand_CreateReg0(Inst, Regs[RegNo]);
161 static DecodeStatus DecodeCRRCRegisterClass(MCInst *Inst, uint64_t RegNo,
165 return decodeRegisterClass(Inst, RegNo, CRRegs);
168 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst *Inst, uint64_t RegNo,
172 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
175 static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, uint64_t RegNo,
179 return decodeRegisterClass(Inst, RegNo, FRegs);
182 static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo,
186 return decodeRegisterClass(Inst, RegNo, FRegs)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Analysis/ |
| PHITransAddr.cpp | 24 static bool CanPHITrans(Instruction *Inst) {
25 if (isa<PHINode>(Inst) ||
26 isa<GetElementPtrInst>(Inst))
29 if (isa<CastInst>(Inst) &&
30 Inst->isSafeToSpeculativelyExecute())
33 if (Inst->getOpcode() == Instruction::Add &&
34 isa<ConstantInt>(Inst->getOperand(1)))
117 Instruction *Inst = dyn_cast<Instruction>(Addr);
118 return Inst == 0 || CanPHITrans(Inst);
[all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | 118 int processInstruction(MCInst &Inst, OperandVector const &Operands,
352 void addRegOperands(MCInst &Inst, unsigned N) const {
354 Inst.addOperand(MCOperand::createReg(getReg()));
357 void addImmOperands(MCInst &Inst, unsigned N) const {
359 Inst.addOperand(MCOperand::createExpr(getImm()));
362 void addSignedImmOperands(MCInst &Inst, unsigned N) const {
368 Inst.addOperand(MCOperand::createExpr(Expr));
374 Inst.addOperand(MCOperand::createExpr(Expr));
377 void addf32ExtOperands(MCInst &Inst, unsigned N) const {
378 addImmOperands(Inst, N)
[all...] |
| /external/capstone/arch/Sparc/ |
| SparcDisassembler.c | 87 static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo,
96 MCOperand_CreateReg0(Inst, Reg);
101 static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo,
110 MCOperand_CreateReg0(Inst, Reg);
115 static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
124 MCOperand_CreateReg0(Inst, Reg);
129 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
138 MCOperand_CreateReg0(Inst, Reg);
143 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
155 MCOperand_CreateReg0(Inst, Reg)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeAsmBackend.cpp | 59 bool MayNeedRelaxation(const MCInst &Inst) const;
61 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
79 bool MBlazeAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
80 if (getRelaxedOpcode(Inst.getOpcode()) == Inst.getOpcode())
84 for (unsigned i = 0; i < Inst.getNumOperands(); ++i)
85 hasExprOrImm |= Inst.getOperand(i).isExpr();
90 void MBlazeAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
91 Res = Inst;
92 Res.setOpcode(getRelaxedOpcode(Inst.getOpcode()))
[all...] |
