| /external/lisa/libs/utils/platforms/ |
| nexus5x.json | 3 "cores" : [
|
| odroid-xu4.json | 3 "cores" : [
|
| cros-elm.json | 3 "cores" : [
|
| cros-kevin.json | 3 "cores" : [
|
| pixel.json | 3 "cores" : [
|
| hikey960.json | 3 "cores" : [
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| ld-sp-warn-cortex-m3.l | 2 [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
3 [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
|
| ld-sp-warn-cortex-m4.l | 2 [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
3 [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
|
| ld-sp-warn-v7.l | 2 [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
3 [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
|
| ld-sp-warn-v7e-m.l | 2 [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
3 [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
|
| ld-sp-warn-v7m.l | 2 [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
3 [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
|
| ld-sp-warn.l | 2 [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
3 [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
|
| thumb-w-bad.d | 1 #name: Wide instruction rejected in non-Thumb2 cores.
|
| /external/swiftshader/src/Common/ |
| CPUID.cpp | 39 int CPUID::cores = detectCoreCount(); member in class:sw::CPUID
232 int cores = 0; local
244 cores++;
250 cores = sysconf(_SC_NPROCESSORS_ONLN);
253 if(cores < 1) cores = 1;
254 if(cores > 16) cores = 16;
256 return cores; // FIXME: Number of physical cores
261 int cores = 0; local
[all...] |
| /external/toolchain-utils/automation/server/ |
| test_pool.csv | 1 hostname,label,cpu,cores,os,username
|
| /external/v8/tools/ |
| cpu.sh | 18 # $1: How many cores to enable.
40 echo "Reactivating all CPU cores"
46 # $1: How many cores to enable.
47 echo "Limiting to $1 cores"
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Library/DebugSecExtraActionLib/ |
| DebugSecExtraActionLib.c | 26 // When the firmware is built as not Standalone, the secondary cores need to wait the firmware
27 // entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
37 // The secondary cores will execute the firmware once wake from WFI.
92 // into DRAM. The secondary cores are still running. As soon as the first bytes of
93 // the firmware are written into DRAM, the secondary cores will start to execute the
95 // That's why the secondary cores need to be parked in WFI and wake up once the
107 // Signal the secondary cores they can jump to PEI phase
114 // cores would make crash the system by setting their stacks in DRAM before the primary core has not
|
| /external/tensorflow/tensorflow/contrib/tpu/proto/ |
| topology.proto | 9 // The dimensions of the TPU topology, in cores. Typically, this is a 3D
11 // and the minor dimension describes the number of cores on a multicore chip.
|
| /external/toolchain-utils/automation/server/monitor/templates/ |
| machine_list.html | 12 <th>Cores</th>
26 <td>{{ machine.cores }}</td>
|
| /external/toolchain-utils/automation/common/ |
| machine.py | 11 def __init__(self, hostname, label, cpu, cores, os, username):
15 self.cores = cores
45 self.label, 'CPU: %s' % self.cpu, 'Cores: %d' % self.cores, 'OS: %s' %
|
| /external/mesa3d/src/amd/common/ |
| amd_family.h | 29 CHIP_R300, /* R3xx-based cores. */
37 CHIP_R420, /* R4xx-based cores. */
46 CHIP_RV515, /* R5xx-based cores. */
|
| /frameworks/base/libs/hwui/tests/scripts/ |
| prep_marlfish.sh | 10 # silver cores
13 # gold cores
21 # to other cores in the cluster
|
| /device/google/wahoo/lisa/ |
| board.json | 3 "cores" : [
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/ |
| mtcmos.h | 11 * cores in cluster 0 are all powered when the system power on. The System
|
| /external/clang/test/CodeGen/ |
| arm-cortex-cpus.c | 3 // Check that Cortex-M cores don't enable hwdiv-arm (and don't emit Tag_DIV_use)
|
