| /external/valgrind/none/tests/mips64/ |
| shift_instructions.c | 8 DSRAV, DSRL, DSRL32, DSRLV,
107 case DSRAV:
108 TEST1("dsrav $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
110 TEST1("dsrav $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| ashr.ll | 129 ; GP64: dsrav $2, $4, $5
168 ; M3: dsrav $[[T1:[0-9]+]], $4, $7
191 ; GP64-NOT-R6: dsrav $2, $4, $7
198 ; 64R6: dsrav $[[T0:[0-9]+]], $4, $7
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64shift.ll | 13 ; ALL: dsrav
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| mips64shift.ll | 12 ; CHECK: dsrav
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| Mips64InstrInfo.td | 124 def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>;
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 91 dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
94 dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64-el.txt | 99 0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
102 0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
234 0x17 0x08 0xc1 0x03 # CHECK: dsrav $1, $1, $fp
|
| valid-mips64.txt | 114 0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
115 0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
139 0x03 0xc1 0x08 0x17 # CHECK: dsrav $1, $1, $fp
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| valid-mips64r2-el.txt | 105 0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
108 0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
255 0x17 0x08 0xc1 0x03 # CHECK: dsrav $1, $1, $fp
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 95 dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
98 dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 95 dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
98 dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 102 dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
105 dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 111 dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
114 dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 111 dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
114 dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 111 dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
114 dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
|
| /external/llvm/lib/Target/Mips/ |
| Mips64InstrInfo.td | 151 def DSRAV : StdMMR6Rel, shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
579 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
692 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
[all...] |
| MicroMips64r6InstrInfo.td | 55 class DSRAV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrav", 0b010010000>;
254 class DSRAV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsrav", II_DSRAV, sra>;
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 39 dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Disassembler/Mips/mips3/ |
| valid-mips3-el.txt | 81 0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
84 0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
|
| valid-mips3.txt | 80 0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
81 0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| valid-mips4-el.txt | 85 0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
88 0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| valid-mips64r3-el.txt | 102 0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
105 0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| valid-mips64r5-el.txt | 102 0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
105 0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 43 dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 39 dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
