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  /external/vixl/test/aarch32/config/
cond-sp-sp-operand-imm7-t32.json 28 // MNEMONIC{<c>}.N <Rd>, SP #<imm7>
32 "Add", // ADD{<c>}{<q>} {SP}, SP, #<imm7> ; T2
33 "Sub" // SUB{<c>}{<q>} {SP}, SP, #<imm7> ; T1
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/
ldst-reg-pair.s 45 // a variety of values for the imm7 field
46 .irp imm7, -64, -31, -1, 0, 15, 63
49 op3_offset \op, \reg, "(\imm7*\size)"
53 op3_post_ind \op, \reg, "(\imm7*\size)"
57 op3_pre_ind \op, \reg, "(\imm7*\size)"
  /external/v8/src/arm64/
assembler-arm64-inl.h 1121 Instr Assembler::ImmLSPair(int imm7, LSDataSize size) {
1122 DCHECK(((imm7 >> size) << size) == imm7);
1123 int scaled_imm7 = imm7 >> size;
1147 Instr Assembler::ImmHint(int imm7) {
1148 DCHECK(is_uint7(imm7));
1149 return imm7 << ImmHint_offset;
    [all...]
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
maverick.c 124 imm7 (func_arg *arg, insn_data *data) function
125 #define imm7 { imm7 } macro
205 signed immediate generated with imm7. */
208 mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, imm7, \
  /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
README.txt 82 | Ks7 | imm7 | |
83 | KN7 | -imm7 | |
BlackfinInstrInfo.td 82 def imm7 : PatLeaf<(imm), [{return isInt<7>(N->getSExtValue());}]>;
191 [(set DP:$dst, imm7:$src)]>;
754 [(set D:$dst, (add D:$src1, imm7:$src2))]>;
    [all...]
  /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/
arg.go 56 // in the "imm7" field times 8
69 // in the "imm7" field times 4
decode.go 242 imm7 := (x >> 15) & (1<<7 - 1)
243 return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 2)) << 23) >> 23}
247 imm7 := (x >> 15) & (1<<7 - 1)
248 return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 3)) << 22) >> 22}
257 imm7 := (x >> 15) & (1<<7 - 1)
258 return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 2)) << 23) >> 23}
262 imm7 := (x >> 15) & (1<<7 - 1)
263 return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 3)) << 22) >> 22}
272 imm7 := (x >> 15) & (1<<7 - 1)
273 return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 2)) << 23) >> 23
    [all...]
inst.json 137 {"Name":"LDNP","Bits":"00:2|1|0|1|0|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
138 {"Name":"LDNP","Bits":"10:2|1|0|1|0|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
139 {"Name":"LDP","Bits":"00:2|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
140 {"Name":"LDP","Bits":"10:2|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
141 {"Name":"LDP","Bits":"00:2|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
142 {"Name":"LDP","Bits":"10:2|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
143 {"Name":"LDP","Bits":"00:2|1|0|1|0|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
144 {"Name":"LDP","Bits":"10:2|1|0|1|0|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
145 {"Name":"LDPSW","Bits":"0|1|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDPSW <Xt1>, <Xt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
146 {"Name":"LDPSW","Bits":"0|1|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #< (…)
    [all...]
  /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/
arg.go 56 // in the "imm7" field times 8
69 // in the "imm7" field times 4
decode.go 242 imm7 := (x >> 15) & (1<<7 - 1)
243 return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 2)) << 23) >> 23}
247 imm7 := (x >> 15) & (1<<7 - 1)
248 return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 3)) << 22) >> 22}
257 imm7 := (x >> 15) & (1<<7 - 1)
258 return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 2)) << 23) >> 23}
262 imm7 := (x >> 15) & (1<<7 - 1)
263 return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 3)) << 22) >> 22}
272 imm7 := (x >> 15) & (1<<7 - 1)
273 return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 2)) << 23) >> 23
    [all...]
inst.json 137 {"Name":"LDNP","Bits":"00:2|1|0|1|0|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
138 {"Name":"LDNP","Bits":"10:2|1|0|1|0|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
139 {"Name":"LDP","Bits":"00:2|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
140 {"Name":"LDP","Bits":"10:2|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
141 {"Name":"LDP","Bits":"00:2|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
142 {"Name":"LDP","Bits":"10:2|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
143 {"Name":"LDP","Bits":"00:2|1|0|1|0|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
144 {"Name":"LDP","Bits":"10:2|1|0|1|0|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
145 {"Name":"LDPSW","Bits":"0|1|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDPSW <Xt1>, <Xt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
146 {"Name":"LDPSW","Bits":"0|1|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #< (…)
    [all...]
  /external/llvm/lib/Target/Sparc/Disassembler/
SparcDisassembler.cpp 644 unsigned imm7 = 0; local
646 imm7 = fieldFromInstruction(insn, 0, 7);
655 // Decode RS1 | IMM7.
657 MI.addOperand(MCOperand::createImm(imm7));
  /toolchain/binutils/binutils-2.27/gas/config/
bfin-parse.y 214 #define imm7(x) EXPR_VALUE (x)
241 if (imm7 (reg2) != reg1->regno - 1)
    [all...]
  /external/llvm/test/CodeGen/PowerPC/
p8-scalar_vector_conversions.ll 685 ; CHECK-DAG: li [[IMM7:[0-9]+]], 7
686 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]]
696 ; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7
697 ; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]]
719 ; CHECK-DAG: li [[IMM7:[0-9]+]], 7
720 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]]
730 ; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7
731 ; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]]
    [all...]
  /external/vixl/test/aarch32/
test-assembler-cond-sp-sp-operand-imm7-t32.cc 228 #include "aarch32/traces/assembler-cond-sp-sp-operand-imm7-add-t32.h"
229 #include "aarch32/traces/assembler-cond-sp-sp-operand-imm7-sub-t32.h"
  /toolchain/binutils/binutils-2.27/include/opcode/
nds32.h 111 #define N16_TYPE37(op4, rt3, ls, imm7) \
113 | __MF (imm7, 0, 7) | __MF (ls, 7, 1))
  /external/vixl/src/aarch64/
assembler-aarch64.h     [all...]
  /external/llvm/lib/Target/ARM/
Thumb2InstrInfo.cpp 295 // sub sp, sp, #imm7
ARMInstrThumb.td 389 // ADD sp, sp, #<imm7>
399 // SUB sp, sp, #<imm7>
    [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/ARM/
Thumb2InstrInfo.cpp 234 // sub sp, sp, #imm7
ARMInstrThumb.td 327 // ADD sp, sp, #<imm7>
337 // SUB sp, sp, #<imm7>
    [all...]
  /toolchain/binutils/binutils-2.27/opcodes/
bfin-dis.c 94 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
470 #define imm7(x) fmtconst (c_imm7, x, 0, outf) macro
    [all...]
  /external/valgrind/VEX/priv/
guest_arm64_toIR.c 7180 UInt imm7 = INSN(11,5); local
    [all...]
  /external/vixl/tools/
generate_tests.py 656 'test/aarch32/config/cond-sp-sp-operand-imm7-t32.json',

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