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  /external/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.h 23 // in a GR128 pair. Is32Bit says whether we want a GR32 or GR64.
24 inline unsigned even128(bool Is32bit) {
25 return Is32bit ? subreg_hl32 : subreg_h64;
27 inline unsigned odd128(bool Is32bit) {
28 return Is32bit ? subreg_l32 : subreg_l64;
  /prebuilts/go/darwin-x86/src/cmd/compile/internal/ssa/gen/
MIPS64.rules 481 (MOVBload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem)
482 (MOVBUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBUload [off1+off2] {sym} ptr mem)
483 (MOVHload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHload [off1+off2] {sym} ptr mem)
484 (MOVHUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHUload [off1+off2] {sym} ptr mem)
485 (MOVWload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem)
486 (MOVWUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWUload [off1+off2] {sym} ptr mem)
487 (MOVVload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVVload [off1+off2] {sym} ptr mem)
488 (MOVFload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVFload [off1+off2] {sym} ptr mem)
489 (MOVDload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem)
491 (MOVBstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem
    [all...]
AMD64.rules 95 (OffPtr [off] ptr) && config.PtrSize == 8 && is32Bit(off) -> (ADDQconst [off] ptr)
641 (ADDQ x (MOVQconst [c])) && is32Bit(c) -> (ADDQconst [c] x)
644 (SUBQ x (MOVQconst [c])) && is32Bit(c) -> (SUBQconst x [c])
645 (SUBQ (MOVQconst [c]) x) && is32Bit(c) -> (NEGQ (SUBQconst <v.Type> x [c]))
649 (MULQ x (MOVQconst [c])) && is32Bit(c) -> (MULQconst [c] x)
652 (ANDQ x (MOVQconst [c])) && is32Bit(c) -> (ANDQconst [c] x)
662 (MULQconst [c] (MULQconst [d] x)) && is32Bit(c*d) -> (MULQconst [c * d] x)
664 (ORQ x (MOVQconst [c])) && is32Bit(c) -> (ORQconst [c] x)
667 (XORQ x (MOVQconst [c])) && is32Bit(c) -> (XORQconst [c] x)
    [all...]
386.rules 564 (ADDLconst [c] (LEAL [d] {s} x)) && is32Bit(c+d) -> (LEAL [c+d] {s} x)
565 (LEAL [c] {s} (ADDLconst [d] x)) && is32Bit(c+d) -> (LEAL [c+d] {s} x)
570 (ADDLconst [c] (LEAL1 [d] {s} x y)) && is32Bit(c+d) -> (LEAL1 [c+d] {s} x y)
571 (ADDLconst [c] (LEAL2 [d] {s} x y)) && is32Bit(c+d) -> (LEAL2 [c+d] {s} x y)
572 (ADDLconst [c] (LEAL4 [d] {s} x y)) && is32Bit(c+d) -> (LEAL4 [c+d] {s} x y)
573 (ADDLconst [c] (LEAL8 [d] {s} x y)) && is32Bit(c+d) -> (LEAL8 [c+d] {s} x y)
574 (LEAL1 [c] {s} (ADDLconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAL1 [c+d] {s} x y)
575 (LEAL2 [c] {s} (ADDLconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAL2 [c+d] {s} x y)
576 (LEAL2 [c] {s} x (ADDLconst [d] y)) && is32Bit(c+2*d) && y.Op != OpSB -> (LEAL2 [c+2*d] {s} x y)
577 (LEAL4 [c] {s} (ADDLconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAL4 [c+d] {s} x y
    [all...]
ARM64.rules 538 (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
541 (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
544 (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
547 (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
550 (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
553 (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
556 (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
559 (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
562 (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
566 (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2
    [all...]
S390X.rules 98 (OffPtr [off] ptr) && is32Bit(off) -> (ADDconst [off] ptr)
522 (ADD x (MOVDconst [c])) && is32Bit(c) -> (ADDconst [c] x)
525 (SUB x (MOVDconst [c])) && is32Bit(c) -> (SUBconst x [c])
526 (SUB (MOVDconst [c]) x) && is32Bit(c) -> (NEG (SUBconst <v.Type> x [c]))
530 (MULLD x (MOVDconst [c])) && is32Bit(c) -> (MULLDconst [c] x)
537 (AND x (MOVDconst [c])) && is32Bit(c) && c < 0 -> (ANDconst [c] x)
572 (CMP x (MOVDconst [c])) && is32Bit(c) -> (CMPconst x [c])
573 (CMP (MOVDconst [c]) x) && is32Bit(c) -> (InvertFlags (CMPconst x [c]))
604 (ADDconst [c] (MOVDaddr [d] {s} x:(SB))) && ((c+d)&1 == 0) && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x)
    [all...]
  /prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/gen/
MIPS64.rules 481 (MOVBload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem)
482 (MOVBUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBUload [off1+off2] {sym} ptr mem)
483 (MOVHload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHload [off1+off2] {sym} ptr mem)
484 (MOVHUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHUload [off1+off2] {sym} ptr mem)
485 (MOVWload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem)
486 (MOVWUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWUload [off1+off2] {sym} ptr mem)
487 (MOVVload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVVload [off1+off2] {sym} ptr mem)
488 (MOVFload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVFload [off1+off2] {sym} ptr mem)
489 (MOVDload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem)
491 (MOVBstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem
    [all...]
AMD64.rules 95 (OffPtr [off] ptr) && config.PtrSize == 8 && is32Bit(off) -> (ADDQconst [off] ptr)
641 (ADDQ x (MOVQconst [c])) && is32Bit(c) -> (ADDQconst [c] x)
644 (SUBQ x (MOVQconst [c])) && is32Bit(c) -> (SUBQconst x [c])
645 (SUBQ (MOVQconst [c]) x) && is32Bit(c) -> (NEGQ (SUBQconst <v.Type> x [c]))
649 (MULQ x (MOVQconst [c])) && is32Bit(c) -> (MULQconst [c] x)
652 (ANDQ x (MOVQconst [c])) && is32Bit(c) -> (ANDQconst [c] x)
662 (MULQconst [c] (MULQconst [d] x)) && is32Bit(c*d) -> (MULQconst [c * d] x)
664 (ORQ x (MOVQconst [c])) && is32Bit(c) -> (ORQconst [c] x)
667 (XORQ x (MOVQconst [c])) && is32Bit(c) -> (XORQconst [c] x)
    [all...]
386.rules 564 (ADDLconst [c] (LEAL [d] {s} x)) && is32Bit(c+d) -> (LEAL [c+d] {s} x)
565 (LEAL [c] {s} (ADDLconst [d] x)) && is32Bit(c+d) -> (LEAL [c+d] {s} x)
570 (ADDLconst [c] (LEAL1 [d] {s} x y)) && is32Bit(c+d) -> (LEAL1 [c+d] {s} x y)
571 (ADDLconst [c] (LEAL2 [d] {s} x y)) && is32Bit(c+d) -> (LEAL2 [c+d] {s} x y)
572 (ADDLconst [c] (LEAL4 [d] {s} x y)) && is32Bit(c+d) -> (LEAL4 [c+d] {s} x y)
573 (ADDLconst [c] (LEAL8 [d] {s} x y)) && is32Bit(c+d) -> (LEAL8 [c+d] {s} x y)
574 (LEAL1 [c] {s} (ADDLconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAL1 [c+d] {s} x y)
575 (LEAL2 [c] {s} (ADDLconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAL2 [c+d] {s} x y)
576 (LEAL2 [c] {s} x (ADDLconst [d] y)) && is32Bit(c+2*d) && y.Op != OpSB -> (LEAL2 [c+2*d] {s} x y)
577 (LEAL4 [c] {s} (ADDLconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (LEAL4 [c+d] {s} x y
    [all...]
ARM64.rules 538 (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
541 (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
544 (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
547 (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
550 (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
553 (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
556 (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
559 (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
562 (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2)
566 (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2
    [all...]
S390X.rules 98 (OffPtr [off] ptr) && is32Bit(off) -> (ADDconst [off] ptr)
522 (ADD x (MOVDconst [c])) && is32Bit(c) -> (ADDconst [c] x)
525 (SUB x (MOVDconst [c])) && is32Bit(c) -> (SUBconst x [c])
526 (SUB (MOVDconst [c]) x) && is32Bit(c) -> (NEG (SUBconst <v.Type> x [c]))
530 (MULLD x (MOVDconst [c])) && is32Bit(c) -> (MULLDconst [c] x)
537 (AND x (MOVDconst [c])) && is32Bit(c) && c < 0 -> (ANDconst [c] x)
572 (CMP x (MOVDconst [c])) && is32Bit(c) -> (CMPconst x [c])
573 (CMP (MOVDconst [c]) x) && is32Bit(c) -> (InvertFlags (CMPconst x [c]))
604 (ADDconst [c] (MOVDaddr [d] {s} x:(SB))) && ((c+d)&1 == 0) && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x)
    [all...]
  /prebuilts/go/darwin-x86/src/cmd/compile/internal/ssa/
rewriteAMD64.go     [all...]
rewrite386.go 1284 // cond: is32Bit(c+d)
1295 if !(is32Bit(c + d)) {
1305 // cond: is32Bit(c+d)
1318 if !(is32Bit(c + d)) {
1329 // cond: is32Bit(c+d)
1342 if !(is32Bit(c + d)) {
1353 // cond: is32Bit(c+d)
1366 if !(is32Bit(c + d)) {
1377 // cond: is32Bit(c+d)
1390 if !(is32Bit(c + d))
    [all...]
rewriteMIPS64.go     [all...]
  /prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/
rewriteAMD64.go     [all...]
rewrite386.go 1284 // cond: is32Bit(c+d)
1295 if !(is32Bit(c + d)) {
1305 // cond: is32Bit(c+d)
1318 if !(is32Bit(c + d)) {
1329 // cond: is32Bit(c+d)
1342 if !(is32Bit(c + d)) {
1353 // cond: is32Bit(c+d)
1366 if !(is32Bit(c + d)) {
1377 // cond: is32Bit(c+d)
1390 if !(is32Bit(c + d))
    [all...]
rewriteMIPS64.go     [all...]
  /system/core/libunwindstack/include/unwindstack/
Regs.h 54 virtual bool Is32Bit() = 0;
96 bool Is32Bit() override { return sizeof(AddressType) == sizeof(uint32_t); }
Unwinder.h 74 static std::string FormatFrame(const FrameData& frame, bool is32bit);
  /external/swiftshader/src/D3D8/
Direct3DIndexBuffer8.hpp 58 bool is32Bit() const;
  /external/swiftshader/src/D3D9/
Direct3DIndexBuffer9.hpp 58 bool is32Bit() const;
  /system/core/libunwindstack/tests/
RegsFake.h 50 bool Is32Bit() { return false; }
  /external/honggfuzz/
sancov.c 310 bool is32bit = true; local
354 is32bit = true;
356 is32bit = false;
456 if (is32bit) {
568 bool is32bit = true; local
620 is32bit = true;
622 is32bit = false;
635 if (is32bit) {
  /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
SystemZISelDAGToDAG.cpp 609 bool is32Bit = false;
615 is32Bit = true;
628 if (is32Bit)
655 unsigned SubRegIdx = (is32Bit ?
669 unsigned SubRegIdx = (is32Bit ?
689 bool is32Bit = false;
696 is32Bit = true;
715 unsigned SubRegIdx = (is32Bit ?
740 unsigned SubRegIdx = (is32Bit ?
753 unsigned SubRegIdx = (is32Bit
    [all...]
  /system/core/libunwindstack/
Unwinder.cpp 257 return FormatFrame(frames_[frame_num], regs_->Is32Bit());
260 std::string Unwinder::FormatFrame(const FrameData& frame, bool is32bit) {
263 if (is32bit) {

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