| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| reloc-dtprel_lo12-ldst32.s | 5 ldrsw x27, [x4, #:dtprel_lo12:sym]
|
| reloc-dtprel_lo12_nc-ldst32.s | 5 ldrsw x20, [x7, #:dtprel_lo12_nc:sym]
|
| reloc-dtprel_lo12-ldst32.d | 8 0: b980009b ldrsw x27, \[x4\]
|
| reloc-dtprel_lo12_nc-ldst32.d | 8 0: b98000f4 ldrsw x20, \[x7\]
|
| programmer-friendly.d | 9 4: 98000241 ldrsw x1, 4c <\.text\+0x4c>
10 8: 98000007 ldrsw x7, 0 <\.text>
|
| ldst-reg-imm-post-ind.d | 188 2d0: b89007e7 ldrsw x7, \[sp\],#-256
189 2d4: b89557e7 ldrsw x7, \[sp\],#-171
190 2d8: b88007e7 ldrsw x7, \[sp\],#0
191 2dc: b88027e7 ldrsw x7, \[sp\],#2
192 2e0: b88047e7 ldrsw x7, \[sp\],#4
193 2e4: b88087e7 ldrsw x7, \[sp\],#8
194 2e8: b88107e7 ldrsw x7, \[sp\],#16
195 2ec: b88557e7 ldrsw x7, \[sp\],#85
196 2f0: b88ff7e7 ldrsw x7, \[sp\],#255
|
| ldst-reg-imm-pre-ind.d | 188 2d0: b8900fe7 ldrsw x7, \[sp,#-256\]!
189 2d4: b8955fe7 ldrsw x7, \[sp,#-171\]!
190 2d8: b8800fe7 ldrsw x7, \[sp,#0\]!
191 2dc: b8802fe7 ldrsw x7, \[sp,#2\]!
192 2e0: b8804fe7 ldrsw x7, \[sp,#4\]!
193 2e4: b8808fe7 ldrsw x7, \[sp,#8\]!
194 2e8: b8810fe7 ldrsw x7, \[sp,#16\]!
195 2ec: b8855fe7 ldrsw x7, \[sp,#85\]!
196 2f0: b88fffe7 ldrsw x7, \[sp,#255\]!
|
| programmer-friendly.s | 17 ldrsw x1, =0xdeadbeef
18 ldrsw x7, u16_lable + 4
|
| ldst-reg-uns-imm.d | 230 378: b98003e7 ldrsw x7, \[sp\]
231 37c: b98003e7 ldrsw x7, \[sp\]
233 384: b98007e7 ldrsw x7, \[sp,#4\]
234 388: b9800be7 ldrsw x7, \[sp,#8\]
235 38c: b98013e7 ldrsw x7, \[sp,#16\]
238 398: b9bfffe7 ldrsw x7, \[sp,#16380\]
|
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-aarch64/ |
| emit-relocs-536.d | 6 10000: b98005d6 ldrsw x22, \[x14,#4\]
8 10004: b9800628 ldrsw x8, \[x17,#4\]
|
| emit-relocs-536.s | 14 ldrsw x22, [x14, #:dtprel_lo12_nc:v2]
17 ldrsw x8, [x17, #:dtprel_lo12_nc:v3]
|
| emit-relocs-535-overflow.s | 11 ldrsw x2, [x17, #:dtprel_lo12:v2]
|
| emit-relocs-535.s | 10 ldrsw x1, [x19, #:dtprel_lo12:v2]
|
| emit-relocs-535.d | 6 10000: b9800661 ldrsw x1, \[x19,#4\]
|
| pr17415.s | 27 ldrsw x0, [sp,12]
|
| /external/llvm/test/MC/AArch64/ |
| elf-reloc-ldrlit.s | 6 ldrsw x9, some_label
|
| arm64-elf-relocs.s | 170 ldrsw x3, [x4, #:lo12:sym]
173 // CHECK: ldrsw x3, [x4, :lo12:sym]
180 ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
183 // CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
191 ldrsw x3, [x4, :tprel_lo12_nc:sym]
194 // CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
|
| arm64-tls-relocs.s | 143 ldrsw x21, [x20, #:tprel_lo12_nc:var]
146 // CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
267 ldrsw x21, [x20, #:dtprel_lo12_nc:var]
270 // CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
|
| tls-relocs.s | 153 ldrsw x21, [x20, #:dtprel_lo12_nc:var]
157 // CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
355 ldrsw x21, [x20, #:tprel_lo12_nc:var]
359 // CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-extend.ll | 8 ; CHECK: ldrsw x0, [x[[REG1]], w0, sxtw #2]
|
| jump-table.ll | 28 ; CHECK-PIC: ldrsw [[DEST:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #2]
|
| aarch64-fix-cortex-a53-835769.ll | 163 ; CHECK: ldrsw
167 ; CHECK-NOWORKAROUND: ldrsw
183 ; CHECK: ldrsw
187 ; CHECK-NOWORKAROUND: ldrsw
202 ; CHECK: ldrsw
205 ; CHECK-NOWORKAROUND: ldrsw
|
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| objdump_test.go | 140 "ldrsw": "ldursw",
|
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| objdump_test.go | 140 "ldrsw": "ldursw",
|
| /external/valgrind/none/tests/arm64/ |
| memory.c | 178 TESTINST2_hide2("ldrsw x21, [x22, #24]", AREA_MID, x21,x22,0);
186 TESTINST2_hide2("ldrsw x21, [x22, #-24]!", AREA_MID, x21,x22,0);
192 TESTINST2_hide2("ldrsw x21, [x22], #-24", AREA_MID, x21,x22,0);
200 TESTINST2_hide2("ldrsw x21, [x22, #-24]", AREA_MID, x21,x22,0);
215 TESTINST3_hide2and3("ldrsw x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
216 TESTINST3_hide2and3("ldrsw x21, [x22,x23, lsl #2]", AREA_MID, 5, x21,x22,x23,0);
217 TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
218 TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #2]", AREA_MID, 5, x21,x22,x23,0);
219 TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
220 TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #2]", AREA_MID, -5ULL, x21,x22,x23,0)
[all...] |
